Senior Principal Analog/RF Design Engineer (Transceivers)

Qorvo, Inc.; England; On-site; GBP 120,000 - 180,000; Full time

Job summary

Qorvo, Inc. in Reading, UK, is seeking a Senior Principal Analog/RF Design Engineer to deliver the next generation of wireless transceivers for high‑performance applications including UWB. This role offers impact across automotive, mobile, industrial, IoT and consumer segments.

You will lead analog/RF design efforts, mentor staff, collaborate across signal chains, layout, and software teams, and drive design-for-test and reliability in cutting‑edge CMOS processes.

Qualifications

• 15+ years of Analog/RF design experience, or an advanced degree with related experience.
• Strong circuit design expertise for transceivers and high-frequency blocks.
• Excellent teamwork, communication and presentation skills.

Responsibilities

• Create and develop analog/RF systems and subsystems for high‑frequency applications.
• Write verification plans and develop automated test benches.
• Model and verify analog/mixed signal blocks with VerilogA/AMS/Wreal.
• Design and verify Analog/RF blocks to at least 20 GHz using industry tools.
• Collaborate with layout engineers to optimize design and layout.
• Ensure designs follow Design-For-Test, isolation, and power optimization.
• Lead design reviews and mentor engineers and interns.

Skills

Analog/RF Design

Transceivers

Cadence Virtuoso

RF circuit design

Team leadership

Education

Bachelor’s degree in Electronic Engineering

Master’s degree in Electronic Engineering

Tools

Cadence Virtuoso

Momentum

EMX

HFSS

Job description

Qorvo, Inc. in Reading, UK, is seeking a Senior Principal Analog/RF Design Engineer to deliver the next generation of wireless transceivers for high‑performance applications including UWB. This role offers impact across automotive, mobile, industrial, IoT and consumer segments.

You will lead analog/RF design efforts, mentor staff, collaborate across signal chains, layout, and software teams, and drive design-for-test and reliability in cutting‑edge CMOS processes.