Senior IC PDK Development Engineer

Entangled Future; Greater London; Hybrid; GBP 90,000 - 150,000; Full time

Benefits offered by this job

Competitive salary

Share options scheme

Contributory pension

Private Medical Insurance

Life Assurance

Cycle-to-work

Flexible working

Central London Islington location

Job summary

Quantum Motion in London is hiring a Senior IC PDK Development Engineer to architect and maintain PDKs and verification environments for silicon-based quantum chips.

The role requires 5+ years in IC PDK development, Cadence SKILL/PCell and Calibre expertise, and strong analytical and communication skills to collaborate with physics and IC teams in a fast-growing startup.

Qualifications

• Industry degree in Electronic Engineering, IC Layout, Computer Science, or related field.
• 5+ years of hands-on IC PDK development and PDK enablement flow management.
• Proficiency in Cadence SKILL PCell coding and Virtuoso PDK customization.
• Proficiency in Siemens Calibre Physical Verification tools and SVRF Rule writing for DRC/LVS.

Responsibilities

• Architect, build, and maintain custom process design kits (PDKs) and physical verification enablements.
• Collaborate with cross-functional teams across IC engineering and physics.
• Debug complex DRC/LVS issues in analog/mixed-signal or custom digital layouts.
• Engage in peer code and layout reviews and maintain high-quality documentation.

Skills

Cadence SKILL

Virtuoso PDK

Calibre

SVRF Rule Writing

DRC/LVS Debugging

Analytical Skills

Communication

Education

Bachelor's degree in Electronic Engineering or related

Tools

Cadence SKILL/PCell coding

Cadence Virtuoso

Siemens Calibre

Job description

Senior IC PDK Development Engineer at Quantum Motion, London, UK. A senior-level full time position in the IC Engineering team, listed under hardware engineering.

About The Role and Team

Quantum Motion is a fast-growing quantum computing start-up based in London. We are developing quantum processors based on industrial-grade silicon chips, with the potential to radically transform computing power in areas such as materials modelling, medicine, artificial intelligence, and cybersecurity. We operate out of state-of-the-art cryogenic facilities in Islington and bring together an outstanding interdisciplinary team spanning quantum physics to IC design.

Our Team

Since 2021 our team has been listed every year in the “Top 100 Startups worth watching” in the EE Times, and our technology breakthroughs have been featured in The Telegraph, BBC, and the New Statesman. Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We are backed by a world-class group of investors including Bosch Ventures, Porsche SE, Sony Innovation Fund, Oxford Science Enterprises, INKEF Capital, and Octopus Ventures.

We bring together the brightest quantum engineers, integrated circuit (IC) engineers, quantum computing theoreticians, and software engineers to create a unique, world-leading team, working closely together to maximize our combined expertise. Our collaborative and interdisciplinary culture is an ideal fit for anyone who thrives in a cutting-edge research and development environment focused on tackling big challenges and contributing to the development of scalable quantum computers based on silicon technology.

Our team of 100+ is based across London, Sydney, San Sebastian & Maryland (US) with our main hub in our Islington lab.

Functions of the Role

The primary function of this position will be to architect, build, and maintain our custom process design kits (PDKs) and physical verification enablements.

Requirements

• Industry degree qualification in Electronic Engineering, IC Layout, Computer Science, or a related physical science/engineering field.
• 5+ years of hands-on industry experience in IC PDK Development and PDK enablement flow management.
• Demonstrated proficiency in Cadence SKILL PCell coding and Virtuoso PDK customization.
• Demonstrated proficiency in Siemens Calibre Physical Verification tools and SVRF Rule writing (specifically for DRC and LVS decks).
• Proven hands-on experience in complex DRC and LVS error debugging within analog/mixed-signal or custom digital layout environments.
• Strong analytical and problem-solving skills with a high level of self-management, self-motivation, and willingness to engage actively in peer code and layout reviews.
• Excellent verbal and written communication skills to collaborate effectively across multidisciplinary physics and IC engineering teams.

Nice to Have

• Demonstrated experience with advanced deep-submicron CMOS nodes (40nm, 28nm, or below), including familiarity with layout-dependent effects (LOD, WPE, OSE, etc.).
• Expert knowledge of the Cadence Virtuoso Design Environment and Cadence SKILL / SKILL++ programming.
• Expert knowledge of the Siemens Calibre Physical Verification Environment.
• Familiarity with MOSFET device modeling integration (e.g., BSIM, Verilog-A) or cryogenic device enablement.
• General awareness or curiosity regarding semiconductor quantum dots or silicon spin qubit fundamentals.

Benefits

• Be part of a creative, world-leading team
• Competitive salary and share options scheme
• Contributory pension scheme
• Private Medical Insurance
• Life Assurance
• Cycle-to-work Scheme
• Flexible working
• Central London location (Islington)