Senior FPGA Architect – RTL & Verification (Coventry)

ZENOVO LTD; West Midlands; Hybrid; GBP 65,000 - 90,000; Full time

Job summary

ZENOVO LTD in Coventry, UK is seeking an experienced FPGA Design Consultant to deliver end-to-end FPGA solutions across multiple customer projects.

You will define requirements, architect FPGA solutions, and implement RTL using VHDL/Verilog, performing synthesis, timing analysis and verification. The role offers hybrid working arrangements and exposure to Tier 1 development processes across leading OEMs.

Qualifications

• Degree in Electronic/ Electrical/ Computer Engineering or related discipline.
• Strong understanding of digital design principles.
• Commercial FPGA design experience.
• Strong RTL development experience using VHDL and/or Verilog.
• Experience with RTL verification and timing analysis.
• Experience with FPGA simulation and synthesis tools.

Responsibilities

• Analyse requirements and define FPGA solutions.
• Develop FPGA architectures and detailed design specifications.
• Develop RTL using VHDL and/or Verilog.
• Design FPGA modules considering area, speed, power and performance.
• Perform module-level and top-level RTL verification.
• Carry out FPGA synthesis and timing analysis.
• Support power and performance analysis.
• Integrate FPGA designs into target hardware platforms.
• Work closely with hardware, firmware and systems engineers.
• Support technical documentation and design reviews.
• Contribute throughout the full design lifecycle from specification through to implementation and verification.

Skills

Strong RTL development

Digital design principles

Problem-solving

Analytical skills

Education

Engineering degree in Electronic/Electrical/Computer Engineering

Tools

VHDL

Verilog

FPGA simulation tools

FPGA synthesis tools

Job description

ZENOVO LTD in Coventry, UK is seeking an experienced FPGA Design Consultant to deliver end-to-end FPGA solutions across multiple customer projects.

You will define requirements, architect FPGA solutions, and implement RTL using VHDL/Verilog, performing synthesis, timing analysis and verification. The role offers hybrid working arrangements and exposure to Tier 1 development processes across leading OEMs.