Senior FPGA Architect – Compute & Hardware Acceleration

Redline Group - Specialist Recruitment for Technology & Electronics Companies; Oxford; Hybrid; GBP 90,000 - 120,000; Full time

Job summary

Redline Group is seeking a Senior FPGA Engineer – Compute Architecture & Hardware Acceleration to join a technology company in Oxford on a hybrid basis. You will translate complex probabilistic algorithms into efficient FPGA RTL designs and help develop next-generation hardware acceleration solutions.

The role requires strong HDL, FPGA design experience and familiarity with PS/PL architectures, with collaboration across hardware and software teams to define system architecture and ensure timing

Qualifications

• Degree in Electrical or related engineering discipline.
• Proven FPGA digital design experience with high-speed systems.
• Strong HDL experience and RTL development from scratch.

Responsibilities

• Translate probabilistic algorithms from Python, C++, MATLAB into pipelined FPGA RTL designs.
• Design and implement custom digital logic in VHDL from scratch.
• Architect and integrate high-speed data acquisition pipelines with PCIe and high-speed transceivers.
• Collaborate with hardware engineers, software developers, researchers and ASIC architects to define system architecture.
• Develop verification environments and optimise timing, power and resources across multiple clock domains.

Skills

FPGA design

HDL programming

Xilinx Vivado

Zynq PS/PL

Timing closure

CDC awareness

Debugging tools

Fixed-point modelling

Education

Electrical Engineering degree

Tools

Vivado

Vitis

TCL scripting

Job description

Redline Group is seeking a Senior FPGA Engineer – Compute Architecture & Hardware Acceleration to join a technology company in Oxford on a hybrid basis. You will translate complex probabilistic algorithms into efficient FPGA RTL designs and help develop next-generation hardware acceleration solutions.

The role requires strong HDL, FPGA design experience and familiarity with PS/PL architectures, with collaboration across hardware and software teams to define system architecture and ensure timing