Senior FPGA Architect: High-Speed RTL & Compute

Quantum Dice; Oxford; On-site; GBP 75,000 - 120,000; Full time

Job summary

Quantum Dice, based in Oxford, UK, seeks a senior FPGA engineer to translate probabilistic models into high-performance RTL and integrate with analogue front ends.

You will design from scratch in VHDL/Verilog, work with PS/PL architectures, and ensure timing closure across clock domains. Strong HDL, lab debug, and FPGA toolchain experience are essential.

This role offers collaboration with academia and industry, tackling real-world probabilistic computing and ASIC-tapeout preparation.

Qualifications

• Degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of hands-on FPGA digital design experience with high-speed systems.
• Strong HDL coding proficiency and a track record of custom RTL from scratch.
• Practical understanding of PS/PL architectures and bare-metal C/C++ for configuring PL peripherals.

Responsibilities

• Translate probabilistic models into highly pipelined, resource-efficient FPGA RTL.
• Design and implement custom digital logic using VHDL where vendor IP is insufficient.
• Integrate high-speed I/O, ADCs, PCIe, and Ethernet with FPGA platforms.
• Collaborate on high-level system architecture with HW/SW teams and ASIC architects.
• Develop testbenches and lab bring-up procedures for hardware verification.
• Analyse and optimise performance, timing closure, power, and resource usage across clock domains.

Skills

HDL coding

Zynq/PS-PL

Fixed-point arithmetic

Clock domain crossing

Lab debugging

Vivado/Vitis

Bare-metal C/C++

Education

Bachelor's degree in Electrical/Computer Engineering or related

Tools

Xilinx Vivado

Xilinx Vitis

TCL scripting

JTAG debugging

Job description

Quantum Dice, based in Oxford, UK, seeks a senior FPGA engineer to translate probabilistic models into high-performance RTL and integrate with analogue front ends.

You will design from scratch in VHDL/Verilog, work with PS/PL architectures, and ensure timing closure across clock domains. Strong HDL, lab debug, and FPGA toolchain experience are essential.

This role offers collaboration with academia and industry, tackling real-world probabilistic computing and ASIC-tapeout preparation.