Formal Verification Engineer

IC Resources; Reading; Hybrid; GBP 50,000 - 70,000; Full time

Job summary

A semiconductor company is seeking a skilled Formal Verification Engineer to support their European design teams. The role involves creating and applying formal verification methodologies for complex digital blocks, collaborating closely with design teams, and improving verification flows. Ideal candidates should have experience in ASIC or FPGA development, proficiency in assertion-based techniques, and scripting skills for automation. The position is full-time and can be based in several locations across Europe.

Qualifications

• Strong background in formal verification for ASIC or FPGA development.
• Experience using formal verification tools, preferable in Cadence ecosystem.
• Proficiency with assertion-based techniques such as SVA or PSL.

Responsibilities

• Create and apply formal verification methodologies for complex digital blocks.
• Review specifications and RTL to build verification plans.
• Develop and maintain formal environments, assertions, and models.
• Collaborate with design teams to analyze results and close issues.
• Support sign-off processes and improve verification flows.

Skills

Formal verification for ASIC or FPGA development

Assertion-based techniques (SVA, PSL)

Formal verification tools usage

Scripting skills (Python, TCL, Perl)

Digital design and CPU/ISA concepts

Clear communication

Tools

Cadence ecosystem

Job description

Principal Recruitment Consultant at IC Resources - Semiconductor Engineering division

This role can also be based in Northampton, Dortmund, Lausanne and Copenhagen

An established yet fast-scaling semiconductor company known for developing advanced, low-power, high-speed connectivity solutions used in next-generation computing and consumer electronics. They’re looking to expand their formal verification capability and are now hiring a skilled Formal Verification Engineer to support their European design teams.

The formal verification engineer will work closely with design, micro-architecture and verification groups to shape and execute effective formal strategies across complex digital IP. The role can be based in Switzerland, the UK, Germany, or Denmark.

Key Responsibilities

• Create, refine and apply formal verification methodologies for complex digital blocks
• Review specifications and RTL to build well-structured, coverage-driven verification plans
• Develop and maintain formal environments, assertions and models
• Analyse results, identify root causes and collaborate with design teams to close issues
• Support sign-off processes and contribute to improving verification flows and automation

Skills & Knowledge

• Strong background in formal verification for ASIC or FPGA development
• Proficiency with assertion-based techniques (e.g., SVA, PSL)
• Experience using formal verification tools (Cadence ecosystem advantageous but not essential)
• Scripting skills for automation (Python, TCL, Perl or similar)
• Understanding of digital design, CPU/ISA concepts and common bus or interconnect protocols
• Clear communicator with a structured, analytical and cooperative working style

Tel - 01189073075

LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Staffing and Recruiting

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