Senior Digital IC Design Engineer - Flexible, London

Entangled Future; Greater London; Hybrid; GBP 90,000 - 130,000; Full time

Benefits offered by this job

Central London location

Competitive salary

Group private medical insurance

Pension scheme

Flexible working

Cycle-to-work scheme

Job summary

Quantum Motion in London is seeking a Senior Digital IC Design Engineer to advance cryogenic silicon-based qubit control and readout circuitry. You will drive RTL design and mixed-signal verification for high-speed interfaces, with a focus on robust physical implementation from RTL to GDSII.

The role requires 5+ years of hands-on IC design experience, a Master's or PhD in EE, and expertise in Verilog/SystemVerilog, EDA tools, and low-power techniques compatible with cryogenic environments.

Qualifications

• Masters or PhD in Electrical Engineering or related field.
• 5+ years in digital and mixed-signal IC design with at least 2 tape-outs on advanced nodes.
• Proficiency in Verilog and SystemVerilog for RTL development.
• Experience with EDA toolchains for mixed-signal simulation, synthesis and verification.
• Ability to translate RTL into GDSII/OASIS layouts and perform CTS/MCMM STA.
• Experience architecting high-speed serial interfaces (SPI/AXI/SerDes) and FSM control logic.
• Expertise in low-power techniques and thermal management for cryogenic systems.

Responsibilities

• Design and verification of digital IC blocks for cryogenic silicon-based qubits.
• Collaborate with cross-disciplinary teams including quantum engineers and software developers.
• Ensure robust physical design flow from RTL to layout and sign-off.

Skills

Verilog

SystemVerilog

RTL Design

FSM Design

SerDes

GDSII Layout

CTS timing

EDA Tools

Power Optimization

Scripting Python

Education

MSc or PhD EE

Tools

Cadence Virtuoso

Cadence Innovus

Xcelium

Design Compiler

Job description

Quantum Motion in London is seeking a Senior Digital IC Design Engineer to advance cryogenic silicon-based qubit control and readout circuitry. You will drive RTL design and mixed-signal verification for high-speed interfaces, with a focus on robust physical implementation from RTL to GDSII.

The role requires 5+ years of hands-on IC design experience, a Master's or PhD in EE, and expertise in Verilog/SystemVerilog, EDA tools, and low-power techniques compatible with cryogenic environments.