Senior DFT Engineer — Next-Gen ASICs & SoC Test

IC Resources; Cambridge; On-site; GBP 65,000 - 90,000; Full time

Job summary

IC Resources is seeking a DFT Engineer to join a growing ASIC team in Cambridge, delivering robust DFT solutions across the silicon development lifecycle from architecture through production.

You’ll define DFT strategies, integrate scan, MBIST, EDT and IJTAG-based test infrastructure, and collaborate with Design, Verification and Physical Implementation teams to ensure high-quality silicon for volume production. Ideal candidates have hands-on Tessent experience and strong scripting skills.

Qualifications

• Experience working within modern ASIC or SoC development flows.
• Strong experience with Siemens Tessent DFT tools.
• Good understanding of complex DFT challenges, including clocking, reset architecture and IP integration.
• Experience with: ATPG, MBIST, Scan architecture, DFT verification and simulation debug, UPF and low-power verification concepts.
• Good Tcl scripting skills (Python is also beneficial).
• Collaborative approach with excellent troubleshooting and debugging skills.

Responsibilities

• Define DFT strategies at chip, subsystem and IP level.
• Implement structural and functional DFT methodologies across complex ASIC designs.
• Insert and integrate scan, MBIST, EDT, SSN and IJTAG-based test infrastructure.
• Verify DFT implementation and debug related issues throughout the design cycle.
• Support implementation and sign-off, including timing constraints, timing closure, power analysis and formal equivalence checking.
• Work closely with Physical Design and Verification teams to ensure successful integration.
• Support ATPG generation, silicon bring-up and manufacturing test.
• Mentor and support other engineers within the team.

Skills

DFT methodologies

ATPG

MBIST

Scan architecture

Tessent

Python/Tcl scripting

Tools

Tessent DFT tools

UPF

Job description

IC Resources is seeking a DFT Engineer to join a growing ASIC team in Cambridge, delivering robust DFT solutions across the silicon development lifecycle from architecture through production.

You’ll define DFT strategies, integrate scan, MBIST, EDT and IJTAG-based test infrastructure, and collaborate with Design, Verification and Physical Implementation teams to ensure high-quality silicon for volume production. Ideal candidates have hands-on Tessent experience and strong scripting skills.