Senior Design Verification Engineer

JR United Kingdom; Crawley; On-site; GBP 50,000 - 75,000; Full time

Job summary

A leading company in RISC-V technology is seeking a Senior Design Verification Engineer based in Crawley, England. This role involves developing verification infrastructure and working closely with design teams to ensure product quality across various high-impact applications in machine learning and aerospace. Candidates should have strong experience in SystemVerilog, UVM, and verification methodologies.

Qualifications

• Strong proficiency in SystemVerilog and UVM.
• Solid understanding of mixed hardware/software verification approaches.
• Experience with RISC-V architectures preferred.

Responsibilities

• Develop and maintain verification infrastructure.
• Define and implement detailed verification strategies.
• Manage functional and code coverage metrics.
• Troubleshoot and debug issues while tracking progress.

Skills

SystemVerilog

UVM

Verification methodologies

Mixed hardware/software verification

Job description

Social network you want to login/join with:

Senior Design Verification Engineer, crawley, west sussex

col-narrow-left

Client:

Platform Recruitment

Location:

crawley, west sussex, United Kingdom

Job Category:

Other

-

EU work permit required:

Yes

col-narrow-right

Job Views:

9

Posted:

06.06.2025

Expiry Date:

21.07.2025

col-wide

Job Description:

Join an innovative, rapidly expanding company at the forefront of the RISC-V revolution developing IC that has high-impact applications across machine learning, aerospace and automotive.

Flat structure with a highly diverse workload and excellent benefits.

Responsibilities:

• Develop and maintain verification infrastructure in collaboration with design teams and external partners.
• Define and implement detailed verification strategies and architectures to ensure product quality and performance.
• Manage functional and code coverage metrics to track and report progress.
• Troubleshoot, debug and resolve issues while maintaining quality tracking dashboards and automated regression tests.

Requirements:

• Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies.
• A solid understanding of mixed hardware/software verification approaches.
• Experience with RISC-V architectures is preferred.
• Proven ability to work effectively with design teams and external partners to achieve project goals.