Senior SoC IP Verification Architect

Baya Systems; Cambridge; Hybrid; GBP 90,000 - 120,000; Full time

Job summary

Baya Systems in Cambridge, UK is seeking a Senior Hardware Verification Engineer to design and implement high‑quality testbenches for configurable IPs across SOCs. The role combines hands‑on verification with collaboration across design and DV teams in a hybrid work model.

You will develop UVM-based testbenches using SystemVerilog, Verilog, and Python, write test plans, and help validate interconnects, caches, memory subsystems, and NOCs within complex IP blocks.

Qualifications

• BS/MS in Electrical/Computer Engineering or CS.
• 8+ years in block/IP/SOC verification with hands-on experience.
• Proficiency in Verilog and SystemVerilog.
• Experience with UVM-based testbenches.
• Familiarity with EDA tools for simulation and debug.
• Knowledge of ARM AMBA AXI, APB, and AHB protocols; CHI a plus.
• Experience with caches, memory subsystems, interconnects, and NOCs.
• Strong problem-solving, communication and collaboration skills.

Responsibilities

• Create test plans for configurable IPs interfacing SOC/interconnects across SOC, chiplet or multi chiplet systems.
• Write UVM/SystemVerilog code to implement test plans, checkers and scoreboards.
• Collaborate with software teams to define and implement configurable testbenches.
• Work with design and DV engineers to implement the test plan, debug failures, close coverage, etc.

Skills

Verilog

SystemVerilog

UVM-based testbenches

Python

Education

BS/MS in Electrical Engineering / Computer Engineering / Computer Science

Tools

Verilog/SystemVerilog simulators

Job description

Baya Systems in Cambridge, UK is seeking a Senior Hardware Verification Engineer to design and implement high‑quality testbenches for configurable IPs across SOCs. The role combines hands‑on verification with collaboration across design and DV teams in a hybrid work model.

You will develop UVM-based testbenches using SystemVerilog, Verilog, and Python, write test plans, and help validate interconnects, caches, memory subsystems, and NOCs within complex IP blocks.