Senior Design Verification Engineer

JR United Kingdom; Cambridge; On-site; GBP 60,000 - 100,000; Full time

Job summary

An innovative company in Cambridge is seeking a Senior Design Verification Engineer to join their rapidly growing hardware team. This exciting role offers the chance to work on cutting-edge technology in the field of quantum computing, where you'll collaborate with world-class engineers in a dynamic and cross-disciplinary environment. You'll take full ownership of functional verification across hardware systems, define verification strategies, and implement robust test environments. This is a unique opportunity to enhance your skills while contributing to high-performance solutions that push the boundaries of technology.

Qualifications

• Strong experience in functional verification and ownership of verification strategies.
• Expertise in testbench design using UVM or OVM frameworks.

Responsibilities

• Define and own verification plans based on design specifications.
• Develop scalable SystemVerilog testbenches and maintain the verification environment.

Skills

Functional Verification

Testbench Design

SystemVerilog Assertions (SVA)

C Programming

C++ Programming

Python Programming

Tools

UVM

OVM

Job description

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Senior Design Verification Engineer, Cambridge

Client:

IC Resources

Location:

Cambridge

Job Category:

Other

EU work permit required:

Yes

Job Views:

4

Posted:

13.04.2025

Expiry Date:

28.05.2025

Job Description:

Cambridge

I am seeking a Senior Verification Engineer to join a rapidly growing HW Team in Cambridge. You will get the opportunity to work on cutting edge technology and in the area of quantum computing. No prior experience in quantum computing? No problem. You'll learn as you go while working alongside world-class engineers in a truly cross-disciplinary environment.

About the Role

As a Senior Verification Engineer, you’ll take full ownership of functional verification across their hardware systems. You’ll collaborate with a talented team of hardware designers and embedded software engineers to deliver trusted, high-performance solutions—verified from the ground up. With full visibility of the stack, you’ll define verification strategies, implement robust test environments, and ensure confidence in every design you deliver.

What You’ll Do

1. Work closely with hardware designers and system architects to define and own verification plans based on design specifications
2. Develop scalable SystemVerilog testbenches, including checkers, coverage groups, and reference models
3. Design and run self-checking, directed, and randomized tests
4. Maintain the verification environment, including tracking regressions, bugs, and coverage metrics
5. Drive quality and performance across block-level and system-level designs

Core skills

1. Strong commercial experience in functional verification, with ownership of verification strategy and planning
2. Expertise in testbench design using frameworks like UVM or OVM
3. Proficiency with SystemVerilog assertions (SVA)
4. Familiarity with multiple programming languages (e.g., C, C++, Python)

Visa sponsorship will be provided for candidates who require. Please note, you must already be living and working in the United Kingdom.

You must also be prepared to work onsite 3 days per week in Cambridge.

For more information, please contact Rachel Mason at IC Resources.