CPU RTL Design Engineer: High-Perf, Low-Power

Qualcomm; Cambridge; On-site; GBP 90,000 - 130,000; Full time

Benefits offered by this job

Stock bonus

Pension

Education assistance

Relocation support

Insurance

Well-being programs

Stock purchase plan

Bicycle scheme

Job summary

Qualcomm Technologies International Ltd in Cambridge, UK, is recruiting for a CPU Micro-architecture and RTL Design Engineer to partner with chip architects on micro-architecture and early product lifecycle involvement. The role expects expertise in RTL/Silicon design and performance/power trade-offs.

You will own RTL development, explore high-performance strategies, and collaborate with cross-functional teams to deliver timing, area and reliability goals across the design flow.

Qualifications

• Bachelor's degree in Science/Engineering with 4+ years ASIC experience.
• Master's degree with 3+ years ASIC experience.
• PhD with 2+ years ASIC experience.

Responsibilities

• Explore high-performance CPU strategies with the modelling team.
• Develop microarchitecture specifications and detailed design.
• Own RTL development and refinement to meet power, performance, area, timing.
• Support functional verification strategy.
• Support performance verification to ensure RTL meets goals.
• Collaborate with cross-functional teams to deliver design.

Skills

Microprocessor architecture

Verilog / VHDL

Logic design & timing

Low power microarchitecture

High performance CPU techniques

Perl / Python scripting

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

Simulators

Waveform debugging tools

Job description

Qualcomm Technologies International Ltd in Cambridge, UK, is recruiting for a CPU Micro-architecture and RTL Design Engineer to partner with chip architects on micro-architecture and early product lifecycle involvement. The role expects expertise in RTL/Silicon design and performance/power trade-offs.

You will own RTL development, explore high-performance strategies, and collaborate with cross-functional teams to deliver timing, area and reliability goals across the design flow.