Lead Analog Layout Engineer - High-Speed Chip Links

Kandou AI; Reading; On-site; GBP 90,000 - 130,000; Full time

Job summary

Kandou AI in Reading is seeking an Analog Layout Engineer (Lead) to drive custom analog layout, verification, and IP integration for high-speed communication links across advanced nodes. You will collaborate with design teams and customers to implement robust, energy-efficient layouts.

The role requires expertise in HF/RF analog blocks, layout techniques for high-speed circuits, and experience with Cadence Virtuoso, Spectre/HSpice, and Calibre.

Qualifications

• Must have experience in custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or HF/RF circuits.
• Must have expertise in layout of high-speed/frequency circuits like amplifiers, oscillators, phase-locked loops, delay-locked loops, and other building blocks (biasing, buffers, regulators, filters, data converters).
• Understanding of layout approaches and techniques for high-speed circuits, matching constraints, minimization of parasitics, power grids and ESD requirements.
• Experience on modern semiconductor process technologies including 28nm, 14/16nm, 7nm.
• User of EDA tool for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop, ESD, etc.

Responsibilities

• Position in custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high speed chip-to-chip communication links (SerDes up to and beyond 28Gb/s and/or memory IO) in advanced semiconductor technology nodes.
• Layout and verification of very high-speed analog circuits.
• Interact closely with the design team to understand requirements and implement solutions.
• Support IP and chip level integration.
• Support and interact with customers on requirements, and IP delivery.
• Exposure to flip-chip package technologies.

Skills

Self-motivated

Good communicator

Team player

Workload management

Semiconductor physics

Education

Graduate in E.E.

Tools

Cadence Virtuoso

Spectre/HSpice

Calibre/PVS

Job description

Kandou AI in Reading is seeking an Analog Layout Engineer (Lead) to drive custom analog layout, verification, and IP integration for high-speed communication links across advanced nodes. You will collaborate with design teams and customers to implement robust, energy-efficient layouts.

The role requires expertise in HF/RF analog blocks, layout techniques for high-speed circuits, and experience with Cadence Virtuoso, Spectre/HSpice, and Calibre.