Senior Analog ASIC Lead Engineer

Renesas; City of Edinburgh; On-site; GBP 70,000 - 95,000; Full time

Benefits offered by this job

Competitive benefits package

International travel opportunities

Job summary

Renesas in the United Kingdom is seeking a senior analog IC design engineer to lead CMOS block design for custom ASICs in a fast-paced environment. You will verify blocks like amplifiers, oscillators, LDOs, and reference circuits, while guiding layout and collaborating with DFT and test teams.

The role requires 5–8 years’ hands-on analog experience, Cadence/EDA proficiency and strong English communication. Occasional international travel and mentoring responsibilities are included.

Qualifications

• Degree in Electronics/Microelectronics required.
• 5–8 years of analog circuit design experience.
• Hands-on design and verification of blocks like amplifiers, oscillators, LDOs, comparators, bias/reference circuits.
• Expertise in filters, PLLs, or RF circuits (advantage).
• Subsystem and chip‑level verification incl. AMS.
• Strong experience with Cadence/EDA tools.
• Ability to work with minimal instruction, independently or in teams.
• Willingness for occasional international travel; strong English communication.

Responsibilities

• Design and verify CMOS analog blocks for custom ASICs to meet performance, area, power and timescale constraints.
• Take technical leadership for sub-systems from spec to production ramp.
• Collaborate with project leads on system and design strategy for custom ASICs.
• Guide layout team to ensure quality of layout of own designs.
• Produce high quality documentation for designed circuits.
• Work with DFT engineers to align to DFT strategy and implementation.
• Drive silicon debugging and design characterization.
• Support lab evaluation and test development for ramp to production.
• Coach and mentor less experienced team members.
• Proactively plan personal development with team input.

Skills

Analog circuit design

AMS verification

Cadence tools

EDA tools

Mentoring

English communication

Education

Bachelor's degree in Electronics/Microelectronics

Tools

Cadence design environment

Job description

Renesas in the United Kingdom is seeking a senior analog IC design engineer to lead CMOS block design for custom ASICs in a fast-paced environment. You will verify blocks like amplifiers, oscillators, LDOs, and reference circuits, while guiding layout and collaborating with DFT and test teams.

The role requires 5–8 years’ hands-on analog experience, Cadence/EDA proficiency and strong English communication. Occasional international travel and mentoring responsibilities are included.