Senior AI Accelerator ASIC Engineer

Ecarx Co.; Greater London; On-site; GBP 120,000 - 180,000; Full time

Job summary

Ecarx Co. is seeking an experienced Senior ASIC Design Engineer to contribute to architecture, microarchitecture, and RTL development for AI accelerators and high-performance SoCs.

You will translate specs into synthesizable RTL, optimize for PPA, and support the full ASIC lifecycle in a collaborative team. The role focuses on hands-on digital design, RTL implementation, debugging, and close collaboration with architecture, verification, and physical design teams to deliver production-quality

Qualifications

• Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field.
• 5+ years hands-on experience in digital ASIC/SoC design, microarchitecture, and RTL implementation.
• Strong architecture/microarchitecture knowledge with hands-on design in GPU/NPU/complex SoC architectures.
• Proficient in Verilog/SystemVerilog RTL design and translating specs into microarchitecture.
• Experience with RTL simulation, synthesis, lint and timing analysis.

Responsibilities

• Develop detailed microarchitecture specifications based on system requirements.
• Design and implement complex digital logic using Verilog/SystemVerilog.
• Develop high-performance datapaths, control logic, FSMs, arbitration, and interfaces.
• Optimize RTL for timing, power, and area; perform RTL reviews and debugging.
• Collaborate with architecture/verification/physical design to deliver production-quality silicon.
• Design and implement functional blocks for AI accelerators, GPU, NPU, or SoC subsystems.
• Develop memory interfaces, DMA engines, and interconnect fabrics.
• Interface with IP and system integration teams to ensure correct interfaces.
• Support silicon bring-up, post-silicon validation, and hardware/software integration.
• Participate in ASIC development lifecycle from spec to tape-out and post-silicon steps.

Skills

ASIC/SoC design

Verilog/SystemVerilog

RTL debugging

Microarchitecture

GPU/NPU architectures

Education

Bachelor’s or Master’s in EE/CE/CS

Tools

Synthesis tools (e.g., Synopsys)

RTL linting tools

Job description

Ecarx Co. is seeking an experienced Senior ASIC Design Engineer to contribute to architecture, microarchitecture, and RTL development for AI accelerators and high-performance SoCs.

You will translate specs into synthesizable RTL, optimize for PPA, and support the full ASIC lifecycle in a collaborative team. The role focuses on hands-on digital design, RTL implementation, debugging, and close collaboration with architecture, verification, and physical design teams to deliver production-quality