Secure SoC/ASIC Verification Engineer

ZeroRISC Inc.; West of England; On-site; GBP 65,000 - 90,000; Full time

Job summary

zeroRISC is seeking a SoC/ASIC Design Verification Engineer to develop, verify, and maintain silicon with a focus on root-of-trust security. You will work from architecture through tapeout and silicon validation, building robust testbenches and verification plans.

You will collaborate with customers and open-source silicon contributors, helping to advance secure silicon IP across hardware and software boundaries in a fast-paced startup environment.

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Science or related field.
• 4 years of verification experience with UVM/SystemVerilog or formal methods.
• Experience developing verification testbenches and environments.

Responsibilities

• Verify ASIC/SoC functionality, performance, security, and power across the full design life cycle.
• Build verification environments at chip/top and block levels.
• Write verification documentation including test plans.
• Diagnose, debug, and resolve regression failures.
• Achieve coverage closure.
• Coordinate with architecture, design, software, system and silicon validation teams and program managers.

Skills

UVM

SystemVerilog

Formal verification

Testbenches

Education

Bachelor’s degree in Electrical Engineering or Computer Science

Equivalent experience

Tools

Python

Job description

zeroRISC is seeking a SoC/ASIC Design Verification Engineer to develop, verify, and maintain silicon with a focus on root-of-trust security. You will work from architecture through tapeout and silicon validation, building robust testbenches and verification plans.

You will collaborate with customers and open-source silicon contributors, helping to advance secure silicon IP across hardware and software boundaries in a fast-paced startup environment.