Enable job alerts via email!

Principal Digital (RTL) Design Engineer

Onsemi

Bracknell

On-site

GBP 50,000 - 80,000

Full time

19 days ago

Boost your interview chances

Create a job specific, tailored resume for higher success rate.

Job summary

Onsemi is seeking a Principal Digital Design Engineer in Bracknell to design and verify digital front-end sub-systems of CMOS imaging sensors and ASICs. The position involves RTL design from requirements analysis to implementation. Candidates should possess relevant industry experience, especially in automotive applications, and expertise in SystemVerilog and digital verification techniques.

Qualifications

  • Fluency in English (written and spoken).
  • Experience in digital design, verification, and maintaining design processes.
  • Knowledge of automotive ADAS, CMOS image sensors, and UVM is a plus.

Responsibilities

  • Design digital front-end sub-systems of CMOS imaging sensors/ASICs.
  • Conduct block and top-level verification and synthesis.
  • Work within established processes for design quality improvements.

Skills

SystemVerilog
Digital Circuit Design
Digital Verification
Scripting Languages
Leadership

Education

Bachelor's/Master's in Electronics/Computing

Tools

Linux
tcl
Perl
Python

Job description

Social network you want to login/join with:

Principal Digital (RTL) Design Engineer, Bracknell

Client: onsemi

Location: Bracknell

Job Category: Other

EU work permit required: Yes

Job Reference: aa54a36888c9
Job Views: 6
Posted: 02.06.2025
Expiry Date: 17.07.2025
Job Description:

Job Summary:

onsemi is seeking a self-starter to join an established team designing and verifying digital front-end sub-systems of CMOS imaging sensors/ASICs. The role involves all aspects of front-end RTL design and verification, from analyzing requirements and producing design documents to coding and verification, then handing off to back-end synthesis and implementation teams. The ideal candidate should have experience designing and verifying low-level blocks for ASIC environments, preferably for automotive applications.

Performance Objectives

The successful candidate will participate in the following activities:

  • Digital design using RTL coding, block and top-level verification, digital constraints, synthesis, ATPG, STA, etc.
  • Expertise in SystemVerilog and RTL design and verification
  • Coding skills in tcl/perl/Python and Verilog/SystemVerilog RTL
  • Experience in maintaining design processes

Added Value

  • Knowledge of CMOS image sensors
  • Understanding of designing for the automotive ADAS market
  • Ability to work independently and support remote design teams
  • Leadership in process and quality improvements

Requirements:

  • Bachelor's/Master's in Electronics/Computing
  • Fluency in English (written and spoken)
  • Knowledge of SystemVerilog, digital circuit design (state machines, control logic, filters, memory interfaces), digital verification (randomized testing, code coverage, verification), UVM (a plus), logic synthesis, DFT, ATPG, STA skills (a plus), Linux, and scripting languages (Perl, Python, shell, tcl)
Get your free, confidential resume review.
or drag and drop a PDF, DOC, DOCX, ODT, or PAGES file up to 5MB.

Similar jobs

Part Time Principal Design Engineer

ZipRecruiter

Luton

Remote

GBP 72,000 - 108,000

9 days ago

Principal High-Speed Digital Electronics Design Engineer

Leonardo UK Ltd

Easter Howgate

Hybrid

GBP 55,000 - 75,000

Yesterday
Be an early applicant

Service Design Consultant

JR United Kingdom

Bedford

Remote

GBP 46,000 - 55,000

10 days ago

Principal Highway Design Engineer

Strata Construction Consulting

Fleet

On-site

GBP 55,000 - 65,000

Yesterday
Be an early applicant

Lead Design Engineer

Bennett And Game Recruitment

Haywards Heath

On-site

GBP 50,000 - 60,000

Yesterday
Be an early applicant

Lead Design Engineer

Mitsubishi Power Europe

London

On-site

GBP 50,000 - 75,000

Yesterday
Be an early applicant

Lead FPGA Design Engineer

Octagon Group

Southampton

Hybrid

GBP 75,000 - 75,000

Yesterday
Be an early applicant

Principal Design Engineer

JR United Kingdom

City Of London

On-site

GBP 50,000 - 80,000

2 days ago
Be an early applicant

M365 Lead Design Engineer

OneSavings Bank PLC

Chatham

Hybrid

GBP 70,000 - 77,000

2 days ago
Be an early applicant