Physical Integration Lead

Ecarx Co.; Greater London; On-site; GBP 120,000 - 180,000; Full time

Job summary

Ecarx Co. in London seeks an experienced Physical Integration Lead to own end-to-end physical design integration of AI SoCs, including floorplanning, top-level PnR, power grid, and physical verification sign-off.

You will mentor a small team of physical design engineers, collaborate with architecture and verification groups, and drive tapeout readiness and flow automation.

The role requires 10+ years in physical design, 7nm+ experience, and proficiency with Calibre/ICV/Pegasus are required.

Qualifications

• 10+ years of experience in physical design / physical integration of complex SoCs.
• Deep expertise in full-chip floorplanning, PnR, clock tree synthesis, and timing closure.
• Hands-on experience with physical verification tools (Calibre, ICV, or Pegasus).
• Proven track record of multiple successful tapeouts (at least 2 full-chip tapeouts in a lead role).
• Experience with advanced process nodes (7nm or below).
• Strong scripting skills (TCL, Python, Perl) for flow automation and debug.
• Experience leading or mentoring engineers — technical leadership ability.
• BSc or higher in Electrical Engineering, Computer Engineering, or related field.

Responsibilities

• Lead full-chip physical integration — floorplanning, power grid design, block partitioning, pin placement, and top-level PnR
• Own end-to-end physical verification sign-off (DRC, LVS, ERC, antenna) at block and full-chip level
• Drive timing closure (STA), power analysis, and IR drop / EM analysis from top-level perspective
• Manage and mentor a team of physical design engineers — setting priorities, reviewing work, and developing technical skills
• Collaborate with architecture, design, verification, and DFT teams to ensure physical implementation feasibility
• Define and enforce physical design methodology, flow, and quality criteria across the team
• Own the tapeout checklist, closure tracking, and sign-off readiness reviews
• Drive continuous improvement of physical design flows, automation scripts, and methodology
• Interface with foundry, packaging, and external IP vendors on physical integration matters

Skills

Physical design leadership

Full-chip floorplanning

PnR (Place & Route)

Timing closure (STA)

Power grid design

Scripting (TCL, Python, Perl)

Team mentoring

Inter-team collaboration

Tapeout readiness

EDA knowledge

Education

BSc or higher in Electrical/Computer Engineering

Tools

Calibre

ICV

Pegasus

Job description

We are looking for an experienced Physical Integration Lead to own the end-to-end physical design integration of our AI SoC devices. You will lead full-chip floorplanning, top-level place-and-route, power grid design, and physical verification sign-off for advanced-node AI chips. This is a hands-on leadership role where you will manage a small team of physical design engineers and drive tapeout readiness across multiple complex IP blocks and subsystems.

Responsibilities

• Lead full-chip physical integration — floorplanning, power grid design, block partitioning, pin placement, and top-level PnR
• Own end-to-end physical verification sign-off (DRC, LVS, ERC, antenna) at block and full-chip level
• Drive timing closure (STA), power analysis, and IR drop / EM analysis from top-level perspective
• Manage and mentor a team of physical design engineers — setting priorities, reviewing work, and developing technical skills
• Collaborate with architecture, design, verification, and DFT teams to ensure physical implementation feasibility
• Define and enforce physical design methodology, flow, and quality criteria across the team
• Own the tapeout checklist, closure tracking, and sign-off readiness reviews
• Drive continuous improvement of physical design flows, automation scripts, and methodology
• Interface with foundry, packaging, and external IP vendors on physical integration matters

Qualifications

• 10+ years of experience in physical design / physical integration of complex SoCs
• Deep expertise in full-chip floorplanning, PnR, clock tree synthesis, and timing closure
• Strong hands-on experience with physical verification tools (Calibre, ICV, or Pegasus)
• Proven track record of multiple successful tapeouts (at least 2 full-chip tapeouts in a lead role)
• Experience with advanced process nodes (7nm or below)
• Solid understanding of power distribution networks, IR drop analysis, and EM verification
• Strong scripting skills (TCL, Python, Perl) for flow automation and debug
• Experience leading or mentoring engineers — technical leadership ability
• BSc or higher in Electrical Engineering, Computer Engineering, or related field

Preferred Qualifications

• Experience with AI accelerator / GPU / high-performance compute chips
• Experience with advanced packaging (2.5D / 3D-IC, chiplet integration)
• Knowledge of low-power design techniques (UPF/CPF, power gating, DVFS)
• Experience with formal verification (LEC, Conformal) for physical design
• Previous experience at semiconductor companies (ARM, NVIDIA, AMD, Qualcomm, Graphcore)
• Familiarity with EDA tool flow development and methodology teams