AI Accelerator Architect

Ecarx Co.; Greater London; On-site; GBP 110,000 - 190,000; Full time

Job summary

Ecarx Co. is seeking a Principal ASIC Design Engineer to lead architecture, microarchitecture, and RTL development for next-generation AI accelerators and high-performance SoC subsystems in the UK.

The role emphasizes hands-on design of complex digital datapaths, memory hierarchies, and high-speed interfaces, with collaboration across system architects, firmware, verification, and physical design teams to deliver production-grade silicon.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

Responsibilities

• Develop AI accelerator architectures and microarchitectures for high-performance subsystems.
• Translate system requirements into detailed functional and microarchitecture specs.
• Design complex digital datapaths, control logic, arbitration, and interfaces.
• Implement RTL in Verilog/SystemVerilog with efficient pipelining and memory subsystems.
• Collaborate with verification, physical design, and software teams to ensure production-quality silicon.

Skills

ASIC/SoC design

RTL design

Verilog/SystemVerilog

PPA optimization

Memory interconnects

NoC architectures

GPU/NPU/AI accelerator

HW/SW co-design

Education

Bachelor's/Master's in Electrical/CS/CE

Tools

UVM verification

FPGA prototyping

Emulation

Formal verification

Job description

We are seeking an experienced Principal ASIC Design Engineer to contribute to the architecture, microarchitecture, and RTL development of next-generation AI accelerators and high-performance SoC subsystems.

The ideal candidate will have extensive hands-on design experience in GPU, NPU, or complex SoC subsystems, with a proven track record of delivering advanced ASIC products from initial specification through RTL implementation, verification, physical design, silicon bring-up, and production.

This position focuses on hands-on engineering, complex digital design, performance optimization, and implementation of advanced computing and interconnect architectures.

Responsibilities

1. AI Accelerator and SoC Architecture

• Develop architecture and microarchitecture for high-performance AI accelerators and complex SoC subsystems.
• Translate system-level requirements into detailed functional and microarchitecture specifications.
• Design compute pipelines, memory hierarchies, on-chip interconnects, DMA engines, and data movement architectures.
• Evaluate design trade-offs involving performance, power, area (PPA), memory bandwidth, latency, and scalability.
• Collaborate with system architects, algorithm engineers, and software engineers to optimize hardware implementations for AI/ML workloads.

2. Microarchitecture and RTL Design

• Develop detailed microarchitecture specifications and synthesizable RTL implementations using Verilog/SystemVerilog.
• Design complex digital datapaths, control logic, finite state machines, arbitration mechanisms, and communication interfaces.
• Implement efficient pipelining, buffering, flow control, and resource-sharing mechanisms.
• Optimize RTL for timing, power, area, and implementation feasibility.
• Perform RTL simulation, debugging, lint, clock-domain crossing (CDC) analysis, and synthesis-related design checks.
• Work with verification and physical design engineers to resolve functional, timing, and implementation issues.

3. High-Speed Interfaces and Memory Subsystems

• Design and integrate high-bandwidth memory and high-speed I/O subsystems.
• Work with memory interfaces and controllers, including LPDDR5/LPDDR5X and LPDDR6.
• Design or integrate PCIe-based subsystems, including PCIe Gen5/Gen6 controllers, DMA engines, and associated data movement infrastructure.
• Understand NoC architectures, memory hierarchies, cache coherency, and bandwidth optimization.
• Optimize data movement and memory access efficiency for high-performance computing and AI accelerator applications.

4. ASIC Development from Specification to Production

• Participate in the complete ASIC development lifecycle, from specification and microarchitecture through RTL design, verification, synthesis, physical implementation, tape-out, and silicon validation.
• Develop production-quality RTL that meets functional, performance, power, and area requirements.
• Collaborate with verification engineers on block-level and SoC-level verification plans, test cases, and functional coverage.
• Support lint, CDC/RDC analysis, formal verification, synthesis, static timing analysis, and design-for-test activities.
• Debug functional and timing issues identified during simulation, emulation, FPGA prototyping, and physical implementation.
• Support silicon bring-up, post-silicon debugging, performance characterization, and production validation.

5. Hardware/Software Co-Design and Verification

• Collaborate with firmware, driver, compiler, and system software engineers to define and implement hardware/software interfaces.
• Participate in hardware/software partitioning and optimization for AI accelerator applications.
• Develop register interfaces, control/status mechanisms, interrupt handling, and system-level data flows.
• Support IP-level and SoC-level functional verification using simulation, emulation, and FPGA prototyping.
• Debug hardware/software integration issues and contribute to system-level validation.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 10+ years of hands-on experience in digital ASIC/SoC microarchitecture and RTL design.
• Demonstrated design experience in at least one of the following: GPU or parallel computing architectures; NPU, AI accelerator, or machine learning processor architectures; Complex SoC subsystems, such as memory controllers, interconnect fabrics, DMA engines, or high-performance processing subsystems
• Proven experience developing ASIC/SoC designs from specification through tape-out and silicon production.
• Strong expertise in microarchitecture development and RTL design using Verilog/SystemVerilog.
• Solid understanding of digital datapaths, control logic, pipelining, memory subsystems, on-chip interconnects, and clock/reset architectures.
• Working knowledge of PCIe and LPDDR memory technologies, including controller architecture, integration, and system-level considerations.
• Experience in at least one of the following: Hardware/software co-design and system integration; IP-level or SoC-level functional verification
• Familiarity with ASIC design methodologies and tools, including RTL simulation, synthesis, static timing analysis, lint, and CDC.
• Strong debugging, analytical, and problem-solving skills.
• Ability to independently develop, implement, and debug complex ASIC functional blocks and subsystems.

Preferred Qualifications

• Direct experience designing GPU, NPU, AI accelerator, or heterogeneous computing SoCs.
• Experience with chiplet architectures and die-to-die interconnects.
• Experience with PCIe Gen5/Gen6 and advanced memory technologies such as LPDDR6.
• Knowledge of NoC architectures, cache coherency, memory consistency, and multi-die system architectures.
• Experience with high-bandwidth data movement, DMA engines, and accelerator memory optimization.
• Understanding of AI/ML workloads, including matrix multiplication, tensor operations, transformer models, and inference acceleration.
• Familiarity with AMBA AXI/ACE/CHI or other industry-standard SoC interconnect protocols.
• Experience with UVM-based verification, formal verification, FPGA prototyping, or hardware emulation.
• Familiarity with advanced semiconductor process technologies, including 7nm, 5nm, 3nm, or below.
• Experience with low-power design techniques, including clock gating, power domains, and power optimization.