PhD Quantum Engineering Internship: QEC & Architecture

Sponsor Finder; Boston; Hybrid; GBP 48,000 - 68,000; Full time

Job summary

Riverlane invites a PhD engineering intern to join our Boston-based project team working at the intersection of quantum error correction and classical architectures. You will explore decoding methods, program architectures, and hardware-software co-design with support from a dedicated supervisor in Cambridge, MA.

Responsibilities include developing algorithms, simulations, and architectural models, collaborating with researchers across disciplines, and producing reproducible research code for

Qualifications

• You must be currently pursuing a PhD in Computer Science, Computer Engineering, Electrical Engineering, Physics, Mathematics or another related technical field.
• Research experience in quantum error correction or fault-tolerant quantum computing is required or highly preferred.
• Experience with computer architecture or quantum-classical systems is desirable.
• Experience with decoding algorithms or error-correcting codes is desired.
• Experience with RTL, SystemVerilog, FPGA or ASIC development workflows is a plus.
• Proficiency in Python, C, C++ or another relevant programming language.

Responsibilities

• Contribute to a research project focused on the classical systems and architectures required for scalable quantum error correction.
• Investigate methods for reducing compute, communication, memory, latency or power requirements in QEC.
• Develop algorithms, simulations or architectural models to evaluate potential approaches.
• Explore trade-offs between decoding performance, logical error suppression and classical resource requirements.
• Consider how QEC workloads could be implemented across software, FPGA, ASIC or other computing architectures.
• Collaborate with researchers and engineers across QEC theory, decoding, software and hardware.
• Analyse results and communicate findings through technical discussions, presentations and reports.
• Produce clear, reproducible research code and supporting documentation.

Skills

Python

C

C++

Research experience

QEC

Computer architecture

Decoding algorithms

Software development

Education

PhD in CS/CE/Physics/Math

Tools

SystemVerilog

FPGA

ASIC

Job description

Riverlane invites a PhD engineering intern to join our Boston-based project team working at the intersection of quantum error correction and classical architectures. You will explore decoding methods, program architectures, and hardware-software co-design with support from a dedicated supervisor in Cambridge, MA.

Responsibilities include developing algorithms, simulations, and architectural models, collaborating with researchers across disciplines, and producing reproducible research code for