Lead Software Engineering - C++

JPMorgan Chase & Co.; Greater London; On-site; GBP 120,000 - 180,000; Full time

Job summary

JPMorgan Chase & Co. in London seeks an Ultra Low Latency Lead Software Engineer to design, build, and operate market gateway solutions with FPGA acceleration, delivering deterministic performance for high-speed trading.

You will collaborate with hardware and software teams, drive latency optimization, implement end-to-end pipelines, and lead development across Unix/Linux environments, CI/CD, and secure engineering practices to support global markets.

Qualifications

• Proficiency in modern C++ on Unix/Linux with multithreading and OO design.
• Hands-on experience in design, development, testing, and production stability.
• Scripting skills (Python, Perl, Shell) for automation.
• Knowledge of Agile, CI/CD, resiliency, and security.

Responsibilities

• Design, build, and operate market gateway solutions with FPGA acceleration.
• Develop high-quality C++ code for trading connectivity and risk controls on Unix/Linux.
• Implement end-to-end low-latency client setups and production rollout.
• Automate remediation to improve operational stability.
• Establish and execute test strategies for latency, throughput, and resiliency.
• Lead adoption of AI-assisted engineering practices with validated outputs.

Skills

Modern C++

Unix/Linux

Multithreading

Python scripting

CI/CD

Networking TCP/IP

AI-assisted tooling

Software-hardware interaction

Leadership

Education

Bachelor's degree in Computer Science or related

Tools

FPGA development

Verilog/VHDL

PCI Express

Linux kernel drivers

FIX/SBE protocols

Job description

Join us to shape the future of electronic trading technology, where your expertise in C++ and hardware acceleration will make a global impact. You’ll collaborate with talented engineers to deliver market-leading solutions that power high-speed trading across global markets. We value creativity, technical excellence, and a passion for continuous improvement. At JPMorganChase, you’ll find opportunities for career growth, skill development, and meaningful contributions. Be part of a team that thrives on solving complex challenges and advancing industry standards.

As an Ultra Low Latency C++ Lead Software Engineer at JPMorgan Chase in the Electronic Trading Technology team, you will design, build, and operate market gateway solutions with hardware FPGA acceleration. You will drive the software development lifecycle, focusing on stability, latency optimization, and continuous improvement. You’ll partner with hardware engineering teams to integrate FPGA pipelines with our C++ software stack, ensuring high reliability and operational excellence. Your work will directly impact trading connectivity and risk management applications used by clients and internal businesses. You’ll help foster a collaborative, innovative team culture.

Job Responsibilities:

• Execute creative software solutions across design, development, and troubleshooting.
• Design, develop, and test reliable, high-quality C++ code for trading connectivity and risk controls on Unix/Linux platforms.
• Implement end-to-end low latency client setups, including production rollout and post-release validation.
• Automate remediation for recurring issues to improve operational stability.
• Establish and execute test strategies for latency, throughput, and resiliency.
• Drives team adoption of enterprise-authorized AI-assisted engineering practices within the work environment to improve code quality, delivery speed, and operational outcomes (e.g., AI-assisted code review/refactoring, test strategy acceleration, incident/root-cause analysis support), while establishing consistent validation standards (secure coding, peer review, automated testing) and promoting reuse of effective patterns across the team.
• Applies knowledge of tools within the Software Development Life Cycle toolchain, including enterprise-authorized AI-assisted development and automation capabilities, to improve the value realized by automation.
• Lead the development of market access trading and risk management modules.
• Participate across the software development lifecycle of electronic trading services.
• Collaborate with Application Development, Business Analysts, and Operations teams.
• Integrate FPGA pipelines with C++ software for deterministic performance.

Required Qualifications, Capabilities, and Skills:

• Proficiency in modern C++ on Unix/Linux with strong multithreading and object-oriented design fundamentals.
• Hands-on experience in system design, application development, testing, and operational stability in production environments.
• Scripting skills (Python, Perl, Shell) for automating development, testing, and operational tasks.
• Advanced understanding of Agile methodologies, including CI/CD, resiliency, and security.
• Ability to review and debug code written by others.
• Knowledge of low-level TCP/IP and network stack behavior.
• Comfort working closely with infrastructure and networking teams.
• Demonstrated experience leading effective use of approved AI-assisted software development tools (e.g., for coding, code review, test acceleration, troubleshooting) with the ability to set team expectations for validating AI outputs for correctness, performance, and security.
• Strong understanding of responsible AI use in engineering workflows, including data sensitivity considerations, secure handling of inputs/outputs, and adherence to resiliency and security expectations; experience coaching engineers on safe, compliant adoption within delivery practices
• Bachelor’s degree in Computer Science, Engineering, Mathematics, or related discipline.
• Excellent understanding of software-hardware interaction.

Preferred Qualifications, Capabilities, and Skills:

• Demonstrated experience in low latency design and development using C/C++, including DMA, exchange connectivity, and pre-trade risk systems.
• Exposure to FPGA development for financial industry applications, including embedded software and kernel driver development for FPGAs and related systems.
• Proficiency with PCI Express, TCP/IP sockets, L1/L3 switches, and integrating C++, Verilog, and VHDL solutions in Linux environments.
• Experience implementing and certifying exchange connectivity using FIX, SBE, and native binary protocols, with a focus on low latency order entry, as well as creating and automating test strategies for functional and non-functional requirements in production-like environments.