IC & PIC Physical Verification Engineer — Tapeout Ready

Salience Labs Ltd; Oxford; On-site; GBP 65,000 - 90,000; Full time

Job summary

Salience Labs Ltd. is seeking a Physical Verification Engineer to drive DRC/LVS signoff for IC and photonic IC designs.

You will work at the intersection of electronic and photonic design, validating layouts and ensuring tapeout cleanliness. The role requires 3+ years of hands-on physical verification experience, proficiency with Calibre or Synopsys ICV for DRC/LVS signoff, GDS/OASIS knowledge, and strong scripting skills in Python/Tcl/Shell.

Qualifications

• 3+ years of hands-on physical verification experience in IC design.
• Proficient with Calibre and/or Synopsys ICV for DRC/LVS signoff.
• Experience with GDS/OASIS formats and LVS concepts.
• Scripting in Python, Tcl, or shell; Linux proficiency.
• Version control experience (Git) and handling libraries/runsets.
• Ability to independently debug hierarchical netlist and layout issues.
• Strong written communication for documenting root causes and fixes.

Responsibilities

• Run and debug physical verification (DRC, LVS, extraction) on IC and photonic IC layouts.
• Debug LVS/DRC discrepancies, including port mismatches, hierarchy mismatches, and device recognition issues.
• Read, manipulate, and QA GDS/OASIS layout data.
• Maintain verification runsets and rule decks.
• Build Python/Tcl/shell tooling to automate verification flows and triage error reports.
• Maintain verification libraries and runsets under version control, with controlled release processes.
• Handle third-party and foundry IP with care, following licensing terms.
• Work with design, layout, and CAD teams to close out verification issues ahead of tapeout.
• Document known issues, workarounds, and runset changes.

Skills

Python

Tcl

Git

Calibre

Synopsys ICV

GDS/OASIS

Tools

Cadence Virtuoso

Synopsys CustomCompiler

Job description

Salience Labs Ltd. is seeking a Physical Verification Engineer to drive DRC/LVS signoff for IC and photonic IC designs.

You will work at the intersection of electronic and photonic design, validating layouts and ensuring tapeout cleanliness. The role requires 3+ years of hands-on physical verification experience, proficiency with Calibre or Synopsys ICV for DRC/LVS signoff, GDS/OASIS knowledge, and strong scripting skills in Python/Tcl/Shell.