GPU Physical Design Engineer — High-Performance

Apple, Inc.; Cambridge; On-site; GBP 70,000 - 110,000; Full time

Job summary

Apple Inc. in Cambridge, UK, seeks a GPU Physical Design Engineer to craft and tape-out next-generation graphics processors. You will translate RTL into robust PD flows and collaborate across Front-End, Back-End, and CAD teams to boost performance and power efficiency.

Responsibilities include driving place & route, floorplanning, and timing sign-off, while solving design and flow issues. A strong background in ASIC implementation and multi‑voltage, multi‑VT strategies is preferred.

Qualifications

• Experience in ASIC implementation: Synthesis, DFT insertion, floorplanning, and timing signoff.
• Knowledge of power distribution, clock distribution, and physical signoff.
• Proven ability to work with Front-End teams on architecture and RTL feedback.

Responsibilities

• Collaborate with Front-End to understand chip architecture and drive physical aspects early.
• Develop PD construction and optimization recipes for performance, power, and area.
• Lead place & route execution and coordinate with top, STA, and P&R teams.
• Resolve design and flow issues related to physical design.
• Drive design methodologies, checklists, and progress tracking.

Skills

ASIC implementation

Synthesis

DFT insertion

Floorplanning

Clock distribution

Power distribution

Place & Route

Timing signoff

Electrical signoff

Physical signoff

Education

BSc/MSEE/M Eng/BEng

Tools

Floorplanning tools

P&R flows

Global timing verification

Physical Design Verification Flows

Job description

Apple Inc. in Cambridge, UK, seeks a GPU Physical Design Engineer to craft and tape-out next-generation graphics processors. You will translate RTL into robust PD flows and collaborate across Front-End, Back-End, and CAD teams to boost performance and power efficiency.

Responsibilities include driving place & route, floorplanning, and timing sign-off, while solving design and flow issues. A strong background in ASIC implementation and multi‑voltage, multi‑VT strategies is preferred.