GPU Modelling Engineer

Apple Inc.; Cambridge; On-site; GBP 110,000 - 150,000; Full time

Job summary

Apple Inc. is seeking a Senior GPU Top Micro-Architect to drive micro-architecture for key IP and system-level improvements within the UK GPU Design Centre.

You will own blocks, contribute to top-level assembly, and collaborate with graphics architecture, verification, and physical design teams to meet performance and power goals. The role requires deep SystemVerilog/VHDL expertise, strong problem-solving skills, and experience with large-scale SoC or GPU design.

Qualifications

• Expertise in SystemVerilog and/or VHDL.
• Strong problem-solving skills and ability to work across teams under aggressive schedules.

Responsibilities

• Develop micro-architecture for owned IP and system-level improvements.
• Design IP blocks and perform synthesis for owned blocks.
• Design clocking and reset distribution; verify CDC/RDC.
• Contribute to GPU top-level assembly/integration.
• Debug and analyze top-level design issues; mentor juniors.

Skills

SystemVerilog/VHDL

Revision control

Scripting languages

GPU/SoC architecture

Tools

Git

Job description

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Senior GPU Top Micro-Architect

The Top Design team at the UK GPU Design Centre works on complex, large-scale GPU related projects. We partner with our graphics architecture, functional verification, and physical design teams to deliver high quality graphics IP in order to meet performance, feature, timing, area and power goals.

Description

The GPU top design team develops micro-architecture and RTL for critical top-level infrastructure IP, and drives micro-architectural improvements across the entire GPU through our holistic system-level perspective.We own complete IP blocks including interconnects, control logic, and clocking/reset distribution. Our unique position working across the full GPU scope enables us to identify optimization opportunities that span multiple units which means our micro-architecture work can influence outside of IP that we own when we identify better system-level solutions.We handle the complete design flow for our IP from concept through physical design handoff, while also contributing to GPU-level assembly and integration.

Responsibilities

• Micro-architecture development (for owned IP and system-level improvements)
• IP design and synthesis (owned blocks)
• Design clocking and reset distribution, perform CDC/RDC verification
• Contribute to GPU top-level assembly/integration
• Debug and analyse top-level design issues
• Codeline management, supporting multiple products & chips
• Review RTL implementations and mentor junior engineers

Minimum Qualifications

• Expertise in SystemVerilog/VHDL and proficiency in revision control systems
• Strong problem-solving skills, ability to work across team boundaries and be productive under aggressive schedules

Preferred Qualifications

• Understanding of computer architecture and physical design
• Experience with large-scale SoC or GPU design
• Experience of scripting languages (for example Python/Ruby/Tcl)

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