Senior GPU Top Design Engineer

Apple Inc.; Greater London; Hybrid; GBP 90,000 - 140,000; Full time

Job summary

Apple Inc. UK GPU Design Centre is seeking an experienced hardware design engineer to drive micro-architecture for top-level IP and perform RTL design and validation. You will work across graphics architecture, verification and physical design teams to meet performance and power goals.

The role focuses on HDL-based IP blocks, clocking/reset distribution, and integration within multi-chips environments, with mentoring of junior engineers and collaboration across shifts and teams.

Qualifications

• Expertise in SystemVerilog/VHDL and revision control.
• Strong problem-solving and cross-team collaboration.

Responsibilities

• Develop micro-architecture for owned IP and system-level improvements.
• Design and synthesize IP blocks with clocking and reset distribution.
• Contribute to GPU top-level assembly and integration.
• Debug and analyse top-level design issues.
• Codebase management supporting multiple products and chips.
• Review RTL implementations and mentor junior engineers.

Skills

SystemVerilog/VHDL

Revision control

Cross-team collaboration

Job description

Selection changes the language of the page/content

The Top Design team at the UK GPU Design Centre works on complex, large-scale GPU related projects. We partner with our graphics architecture, functional verification and physical design teams to deliver high quality graphics IP in order to meet performance, feature, timing, area, and power goals.

Description

The GPU top design team develops micro-architecture and RTL for critical top-level infrastructure IP and drives micro-architectural improvements across the entire GPU through our holistic system-level perspective.We own complete IP blocks including interconnects, control logic and clocking/reset distribution. Our unique position working across the full GPU scope enables us to identify optimization opportunities that span multiple units which means our micro-architecture work can influence outside of IP that we own when we identify better system-level solutions.We handle the complete design flow for our IP from concept through physical design handoff, while also contributing to GPU-level assembly and integration.

Responsibilities

• Micro-architecture development (for owned IP and system-level improvements)
• IP design and synthesis (owned blocks)
• Design clocking and reset distribution, perform CDC/RDC verification
• Contribute to GPU top-level assembly/integration
• Debug and analyse top-level design issues
• Codeline management, supporting multiple products & chips
• Review RTL implementations and mentor junior engineers

Minimum Qualifications

• Expertise in SystemVerilog/VHDL and proficiency in revision control systems
• Strong problem-solving skills, ability to work across team boundaries and be productive under aggressive schedules

Preferred Qualifications

• Understanding of computer architecture and physical design
• Experience with large-scale SoC or GPU design
• Experience of scripting languages (for example Python/Ruby/Tcl)

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