Senior GPU Top Design Engineer

Omaze; Greater London; On-site; GBP 120,000 - 160,000; Full time

Job summary

Apple UK GPU Design Centre is seeking a Senior Engineer for the Top Design team to develop micro-architecture and RTL for critical IP, collaborating across graphics architecture, verification and physical design groups.

You will own IP blocks, drive clocking and reset distribution, and contribute to GPU assembly and integration while mentoring junior engineers and ensuring delivery under tight schedules.

Qualifications

• Expertise in design including logic synthesis.
• Proficiency in SystemVerilog/VHDL and revision control.
• Strong problem-solving and cross-team collaboration under tight schedules.

Responsibilities

• Micro-architecture development for owned IP and system-level improvements.
• IP design and synthesis for owned blocks.
• Design clocking and reset distribution; CDC/RDC verification.
• Contribute to GPU top-level assembly/integration.
• Debug and analyze top-level design issues.
• Prepare deliverables for physical design handoff.
• Code line management, supporting multiple products & chips.
• Review RTL implementations and mentor junior engineers.

Skills

Logic synthesis

SystemVerilog/VHDL

Revision control

Tools

Git

Job description

Summary

The Top Design team at the UK GPU Design Centre works on complex, large-scale GPU related projects. We partner with our graphics architecture, functional verification and physical design teams to deliver high quality graphics IP in order to meet performance, feature, timing, area, and power goals.

Description

The GPU top design team develops micro-architecture and RTL for critical top-level infrastructure IP and drives micro-architectural improvements across the entire GPU through our holistic system-level perspective.

We own complete IP blocks including interconnects, control logic, and clocking/reset distribution. Our unique position working across the full GPU scope enables us to identify optimization opportunities that span multiple units which means our micro-architecture work can influence outside of IP that we own when we identify better system-level solutions.

We handle the complete design flow for our IP from concept through physical design handoff, while also contributing to GPU-level assembly and integration.

Responsibilities

• Micro-architecture development (for owned IP and system-level improvements)


• IP design and synthesis (owned blocks)


• Design clocking and reset distribution, perform CDC/RDC verification


• Contribute to GPU top-level assembly/integration


• Debug and analyse top-level design issues


• Prepare deliverables for physical design handoff


• Codeline management, supporting multiple products & chips


• Review RTL implementations and mentor junior engineers

Minimum Qualifications

• Expertise in design including logic synthesis


• Expertise in SystemVerilog/VHDL and proficiency in revision control systems


• Strong problem-solving skills, ability to work across team boundaries and be productive under aggressive schedules

Preferred Qualifications

• Understanding of computer architecture and physical design


• Experience with large-scale SoC or GPU design


• Experience of scripting languages (for example Python/Ruby/Tcl)

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Role Number: 200644753-2114