FPGA Engineer

Heronic Technologies Limited; Greater London; Hybrid; GBP 60,000 - 90,000; Full time

Job summary

Heronic Technologies Limited in London (UK) is seeking an enthusiastic FPGA Engineer to join a fast-moving team. You will design and implement architecture sub-systems for FPGA deployment and develop FPGA-based systems that leverage our AI accelerator IP.

You will optimise existing RTL designs for FPGA timing, develop register-file specifications and driver code, and collaborate with verification and software teams to ensure robust, high-performance designs.

Qualifications

• Hands-on FPGA debugging experience with Signal Tap or ILA.
• Experience with Altera (Intel) and AMD devices.
• Proficiency with FPGA design tools Quartus and Vivado.

Responsibilities

• Design and implement architecture sub-systems for FPGA deployment.
• Develop FPGA-based systems to exploit AI accelerator IP.
• Optimize RTL designs for FPGA timing; collaborate with verification and software teams.

Skills

FPGA debugging

Memory interfaces

DSP algorithms

Git

Python

Tcl

Cocotb

Verilator

Tools

Quartus

Vivado

Altera/AMD devices

Lattice

Efinix

Achronix

Job description

# FPGA EngineerLondon, UK Full-timeHeronic's purpose is to architect an efficient future for computing through automated, bespoke design. One-size-fits-all GPU/NPU accelerator architectures woefully underutilise available compute; at Heronic we turn the design paradigm on its head, creating specialised architectures that reach near 100% occupancy. With and backing from VCs and Angels including the co-founder of Arm who are active investors in the semiconductor industry, we have the right support, team and technology to deliver the most efficient, competitive AI accelerator architectures ever.We are looking for an enthusiastic FPGA Engineer who is eager to get hands-on with design. You will be instrumental in the process of implementing and refining designs, leveraging a deep familiarity with FPGA fabric that goes beyond general-purpose RTL, to ensure optimal performance. We are seeking someone who enjoys working across the full stack, from high-level system architecture down to the primitives, ensuring our designs are robust and highly efficient.**Key Responsibilities:*** Design and implementation of our architecture sub-systems for FPGA deployment.* Develop FPGA-based systems which can exploit our AI accelerator IP.* Optimise existing RTL designs for FPGA devices, in particular timing.* Develop register file specifications and driver code.* Collaborate with the verification and software teams.**Experience:*** Hands-on experience with debugging FPGA systems with either Signal Tap or ILA.* Has worked with both Altera and AMD devices.* Developed systems that use memory interfaces.* Familiarity with other FPGA vendors (Lattice, Efinix, Achronix) is a plus.* Experience implementing digital signal processing algorithms.* Familiarity with FPGA design tools, specifically Quartus and Vivado.* Familiarity with scripting languages (Python, Tcl).* Comfortable with version control systems (Git).* Comfortable with open-source verification tools (Cocotb, Verilator).**Who You Are:*** Comfortable in a small, fast-moving team.* Willing to adapt to unfamiliar design paradigms.* Strong communicator who can work across teams.* Excited to share knowledge and experience with others.* Curious beyond your discipline, interested in other aspects of the business.