Senior Digital Design Engineer

Heronic Technologies Limited; Greater London; Hybrid; GBP 90.000 - 140.000; Vollzeit

Zusammenfassung

Heronic Technologies Limited in London, UK, seeks a Senior Digital Design Engineer to lead RTL development and help guide our AI accelerator architecture from concept to customer integration.

You will design and implement AI processor components, contribute to architecture roadmaps, and optimise existing RTL designs, balancing performance, power and area while collaborating closely with verification and software teams.

Qualifikationen

• Proficient with hardware design languages (HDL).
• Have taken designs through to silicon (customer-shipped a plus).
• Experience with ASIC and FPGA design.
• Experience implementing digital signal processing algorithms.
• Experience integrating accelerator cores into an SoC architecture (Arm, RISC-V).
• Familiarity with scripting languages (Python, Tcl).
• Comfortable with version control systems (Git) and open-source verification tools (Cocotb, Verilator).

Aufgaben

• Design and implementation of AI processor architecture components.
• Contribute to the architecture roadmap.
• Optimise existing RTL designs.
• Expose design choices for performance, power and area trade-offs.
• Work closely with verification and software teams.
• Document RTL requirements and interfaces.

Kenntnisse

HDL design

ASIC/FPGA design

SoC integration

DSP algorithms

Arm/RISC-V

Python

Tcl

AI workloads

Tools

Git

Cocotb

Verilator

Jobbeschreibung

# Senior Digital Design EngineerLondon, UK Full-timeHeronic's purpose is to architect an efficient future for computing through automated, bespoke design. One-size-fits-all GPU/NPU accelerator architectures woefully underutilise available compute; at Heronic we turn the design paradigm on its head, creating specialised architectures that reach near 100% occupancy. With and backing from VCs and Angels including the co-founder of Arm who are active investors in the semiconductor industry, we have the right support, team and technology to deliver the most efficient, competitive AI accelerator architectures ever.We are looking for an experienced engineer who can help guide and deliver our technical strategy. You will be involved in leading RTL development, contributing to and improving on our efficient and highly configurable architecture components. You should have the confidence to see through a project all the way through from architecture specification to a design integrated and deployed into a customer's system. And the job is never over; you need to have the desire to constantly improve and iterate, as well as communicate these improvements to the rest of the team.**Key Responsibilities:*** Design and implementation of AI processor architecture components.* Contribute to the architecture roadmap.* Optimise existing RTL designs.* Expose design choices for performance, power and area trade-offs.* Work closely with verification and software teams.* Document RTL requirements and interfaces.**Experience:*** Proficient with hardware design languages.* Have taken designs through to silicon (customer-shipped a plus).* Experience with ASIC and FPGA (Altera, AMD, Lattice) design.* Experience implementing digital signal processing algorithms.* Experience integrating accelerator cores into an SoC architecture (Arm, RISC-V).* Familiarity with scripting languages (Python, Tcl).* An understanding of AI workloads and AI accelerator architecture concepts.* Comfortable with version control systems (Git).* Comfortable with open-source verification tools (Cocotb, Verilator).**Who You Are:*** Comfortable in a small, fast-moving team.* Willing to adapt to unfamiliar design paradigms.* Strong communicator who can work across teams.* Excited to share knowledge and experience with others.* Curious beyond your discipline, interested in other aspects of the business.