FPGA Design Engineer: Prototyping & Validation

Normal Computing Corporation; Greater London; On-site; GBP 90,000 - 140,000; Full time

Job summary

Normal Computing in London is seeking an experienced FPGA Design Engineer to bridge RTL and physical silicon. You will bring physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development, and create the test infrastructure for post-silicon bring-up.

You will own FPGA platform selection, RTL adaptation, and integration of in-house designs with vendor IP, collaborating with silicon, EDA, and research teams to push performance and reliability.

Qualifications

• Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware.
• Expert-level SystemVerilog and/or VHDL for synthesis with Xilinx Vivado expertise.
• Hands-on PCIe and common interfaces experience.
• Strong Python for automation, test, and build tooling.
• Strong lab bring-up and hardware debugging skills.
• Startup mindset with independence and ability to tackle ambiguous hardware/software/physics problems.

Responsibilities

• Lead FPGA platform selection, procurement, and bring-up for pre-silicon RTL validation and software development.
• Adapt and implement ASIC RTL onto FPGA targets for validation and early software development.
• Integrate in-house designs with third-party and vendor IP within the Xilinx Vivado ecosystem.
• Design, implement, and validate high-speed PCIe interfaces on accelerator cards.
• Build FPGA-based tester designs for silicon bring-up and device characterization.
• Develop the software layer (Python/C++) to control hardware and automate builds and tests.
• Lab debugging to root-cause timing and functional issues with real hardware.

Skills

FPGA design experience

SystemVerilog/VHDL

PCIe interfaces

Python

Lab debugging

Startup mindset

Tools

Vivado

HAPS

Job description

Normal Computing in London is seeking an experienced FPGA Design Engineer to bridge RTL and physical silicon. You will bring physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development, and create the test infrastructure for post-silicon bring-up.

You will own FPGA platform selection, RTL adaptation, and integration of in-house designs with vendor IP, collaborating with silicon, EDA, and research teams to push performance and reliability.