FPGA and DSP Engineer

Plextek; Great Chesterford; On-site; GBP 60,000 - 90,000; Full time

Job summary

Plextek is seeking an experienced FPGA engineer to design and implement FPGA-based solutions for radar, communications and sensing applications. You will work within a multidisciplinary team to translate customer requirements into robust FPGA-based implementations, primarily targeting AMD (Xilinx) silicon such as Zynq SoC devices.

As part of Plextek, you will collaborate with hardware, software and systems engineers across the full development lifecycle, from concept through validation and

Qualifications

• Experience in HDL-based FPGA design across complex projects.
• Strong background in digital signal processing for FPGA implementations.
• Familiarity with AMD Vivado toolchain and simulation/test workflows.
• Experience with OpenCPI, STICS or SOSA standards is advantageous.
• Experience with other FPGA platforms is a plus.

Responsibilities

• Deliver high-quality FPGA/DSP designs and implementations with minimal supervision.
• Contribute to technical discussions, design reviews, and project planning (including proposals and time estimates).
• Engage with clients on a technical level, including pre-contract scoping discussions and 'the art of the possible'.
• Potentially able to lead and mentor junior colleagues.
• Work effectively within multidisciplinary project teams.

Skills

HDL

Vivado toolchain

OpenCPI

STICS

SOSA

FPGA design

DSP processing

RF systems knowledge

Tools

Vivado

Job description

Plextek is a leading choice for employees and customers for exceptional engineering and strategic innovation to create better safer and more sustainable technologies and products.

OUR VALUES AND BELIEFS

Being a responsible business, we work with integrity and honesty. We share success with our people and our communities. We embrace diversity in outlook and work as a team with colleagues, customers and suppliers to provide the best technical solution and professional service experience. We empower each other, we're adaptable, show initiative and deliver on our commitments together.

THE ROLE

We are looking for an experienced FPGA engineer with strong skills in HDL, the AMD Vivado toolchain, and associated simulation and test. Experience of relevant open architecture standards such as OpenCPI, STICS or SOSA.

We will also consider experience with other FPGA platforms.

The successful candidate will play a key role in developing Plextek IP and delivering a wide range of client projects, predominantly focused on radar, communications and sensing applications. As a result, a solid grounding in digital signal processing is a core requirement, with experience in RF systems considered a significant advantage.

Working within a multidisciplinary consultancy team, you will help translate customer requirements into robust FPGA-based implementations, contributing across the full development lifecycle from concept and architecture through to validation and ongoing support.

Your day-to-day development work will likely be targeted at AMD (Xilinx) silicon, often Zynq SoC devices, and will involve close collaboration with hardware, software and systems engineers on technically demanding programmes. Multidisciplinary experience is therefore highly valued, particularly where candidates are also comfortable working in the electronics and firmware domains. Alternatively, we are interested in candidates with a strong core skill set who are keen to broaden their experience. As with all our engineers, adaptability and a willingness to learn are key attributes across all roles at Plextek.

RESPONSIBILITIES

• Deliver high-quality FPGA/DSP designs and implementations with minimal supervision.
• Contribute to technical discussions, design reviews, and project planning (including proposals and time estimates).
• Engage with clients on a technical level, including pre-contract scoping discussions and "the art of the possible".
• Potentially able to lead and mentor junior colleagues.
• Work effectively within multidisciplinary project teams.