Digital Verification Engineer

microTECH Global Limited; United Kingdom; On-site; GBP 90,000 - 120,000; Full time

Job summary

A leading technology firm is offering an exciting opportunity for a Digital Verification Engineer. This remote role involves ensuring the functional correctness of ASIC designs, developing verification environments using SystemVerilog/UVM, and collaborating with design teams. The ideal candidate will have over 7 years of digital verification experience and strong scripting skills in Python or Perl. This position offers a challenging environment that shapes innovative technology while working with world-class teams.

Qualifications

• 7+ years of hands-on experience in digital verification.
• Expertise in SystemVerilog/UVM.
• Strong digital design knowledge.
• Proficiency with EDA simulation and debug tools.

Responsibilities

• Ensure functional correctness and performance of digital ASIC designs.
• Develop SystemVerilog/UVM verification environments.
• Automate verification flows using Python or Perl.
• Collaborate with design teams to deliver high-quality results.
• Automate verification flows using Python or Perl scripts.

Skills

Digital verification

SystemVerilog/UVM

Scripting (Python, Perl)

EDA simulation tools

Communication skills

Autonomous work

Tools

EDA simulation tools

Job description

Are you passionate about ensuring the functional correctness of complex digital ASIC designs? We have an exciting opportunity for a Digital Verification Engineer to join a dynamic team, working remotely with occasional visits to the London office.

Role

Role: Digital Verification Engineer (Remote)

Location: Remote – occasional travel to London

Rate/Salary: Negotiable

Duration: Permanent

What You’ll Do

• Ensure the functional correctness and performance of complex digital ASIC Core/IP designs, including deep unit and core-level verification.
• Develop robust SystemVerilog/UVM verification environments.
• Create and execute tests to achieve high coverage and debug complex failures.
• Collaborate closely with design teams to deliver high-quality results.
• Automate verification flows using Python or Perl scripts.

What We’re Looking For

• 7+ years of hands‑on experience in digital verification.
• Expertise in SystemVerilog/UVM and strong digital design knowledge.
• Experience verifying digital systems using standard IP components (e.g., microprocessor cores, hierarchical memory subsystems).
• Proficiency with EDA simulation and debug tools.
• Strong scripting skills (Python, Perl).
• Excellent communication skills and ability to work autonomously.

Why This Role is Exciting

This is a fantastic chance to work on high‑impact ASIC designs in a highly autonomous role while collaborating with world‑class design teams. If you’re looking for a challenging, rewarding opportunity where your expertise directly shapes cutting‑edge technology, this is the role for you.

If interested, please get in touch and send over your CV to [e-mail]