Design Verification Engineer

JR United Kingdom; Bradley Stoke; On-site; GBP 40,000 - 60,000; Full time

Job summary

A leading global Semiconductor company in Bristol is seeking a skilled Design Verification Engineer. The role involves developing verification plans, collaborating with teams, and conducting thorough coverage analysis to ensure digital designs meet specifications. Ideal candidates will have relevant degrees and strong experience in UVM and SystemVerilog.

Qualifications

• Solid understanding and hands-on experience with UVM and SystemVerilog.
• Proficiency in scripting languages such as Perl, Python, or TCL.
• Mid-Senior level experience required.

Responsibilities

• Develop and implement verification plans for digital designs using UVM.
• Collaborate with cross-functional teams and understand design requirements.
• Write and maintain verification test benches, test cases, and coverage models.

Skills

UVM

SystemVerilog

Scripting Languages

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field

Job description

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Client:

IC Resources

Location:

bradley stoke, United Kingdom

Job Category:

Other

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EU work permit required:

Yes

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Job Views:

5

Posted:

06.06.2025

Expiry Date:

21.07.2025

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Job Description:

Bristol, UK

I am looking for a skilled Design Verification Engineer to join a dynamic team at a global Semiconductor giant in Bristol. The Design Verification Engineer will be responsible for verifying complex digital designs and ensuring that the functionality and performance meet the required specifications.

Responsibilities

• Developing and implementing verification plans for digital designs using UVM (Universal Verification Methodology)
• Collaborating with cross-functional teams to understand design requirements and contributing to the design verification strategy
• Writing and maintaining verification test benches, test cases, and coverage models
• Performing functional and code coverage analysis to ensure comprehensive verification of the design
• Debugging test failures and working closely with design teams to resolve issues
• Contributing to the improvement of verification processes and methodologies

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
• Solid understanding and hands-on experience with UVM and SystemVerilog
• Proficiency in scripting languages such as Perl, Python, or TCL
• Mid-Senior level

As a Design Verification Engineer, the individual will spend their days collaborating with design and verification teams to ensure successful verification and validation of digital designs. They will write and maintain test cases, analyze code coverage, and participate in debugging and issue resolution activities. The role will also involve contributing to the improvement of verification processes and methodologies and engaging in cross-functional communication to align on design verification strategies.

For more information, please contact Rachel Mason at IC Resources.