Design Verification Engineer

JR United Kingdom; Hounslow; On-site; GBP 40,000 - 70,000; Full time

Job summary

A leading company in the semiconductor field seeks a Design Verification Engineer in southwest London. This role involves verifying CPU connectivity, developing test plans, and ensuring coverage compliance for SoCs. Candidates should have experience with various verification methodologies and proficiency in tools like Verilog and UVM.

Qualifications

• Experience with CPU connectivity verification.
• Proficient in writing test plans and developing test benches.
• Ability to debug test failures and file reports.

Responsibilities

• Verify CPU connectivity to IP blocks using ASM boot and C code.
• Develop tests to meet functional coverage and closure.
• Provide verification reports demonstrating test pass results.

Skills

CPU connectivity

test planning

debugging

coverage analysis

Tools

GNU toolchain

Verilog

System Verilog

UVM

Job description

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Design Verification Engineer, south west london

Client:

ALOIS Solutions

Location:

south west london, United Kingdom

Job Category:

Other

-

EU work permit required:

Yes

Job Views:

1

Posted:

31.05.2025

Expiry Date:

15.07.2025

Job Description:

• Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain)
• The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs/Subsystems
• Run regressions, debug test failures and file bug reports as needed.
• Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps.
• Provide verification reports to demonstrate all implemented tests pass on the RTL.
• Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases.