Design Verification Engineer

IC Resources; Bristol; Hybrid; GBP 60,000 - 85,000; Full time

Job summary

An innovative firm is seeking a Design Verification Engineer to join their dynamic team focused on AI neuromorphic silicon chips. This role involves designing, simulating, and verifying digital blocks in RTL, working closely with a talented group of engineers. You will develop test benches, collaborate on ASIC implementations, and analyze circuits to ensure optimal performance. If you are passionate about cutting-edge technology and eager to make an impact in the semiconductor industry, this is the perfect opportunity for you.

Qualifications

• Experience in RTL design and verification of digital circuits.
• Proficient in developing test benches and test cases for verification.

Responsibilities

• Develop test benches and test cases for block-level functional verification.
• Collaborate with teams to address synthesis and timing issues.
• Analyze circuits for root cause analysis and propose solutions.

Skills

Verilog

SystemVerilog

UVM

EDA tools (Cadence, Mentor)

RTL design/verification

Static timing analysis

Job description

Join to apply for the Design Verification Engineer role at IC Resources

Verification Engineer

Salary: £60,000 - £85,000 DOE

Location: Bristol and/or fully remote within the United Kingdom

Technology: AI Neuromorphic Silicon chips

I am seeking a Digital Verification Engineer to join a dynamic fabless semiconductor team. You will be part of a wider group including Digital, Analog, and Backend Engineers, working on the development of AI neuromorphic chips. Your responsibilities will include designing, simulating, and verifying digital blocks implemented in RTL for various functions such as control state machines, DSP, and multiple clock domain interfaces.

The company's technology enables fast and efficient conversion of trained Neural Networks into compact AI silicon chips with ultra-low power consumption, low latency, and small size.

Key Responsibilities

1. Develop test benches and test cases for block-level functional verification.
2. Collaborate with backend/implementation teams to address synthesis, timing, and DFT issues for ASIC implementation.
3. Define verification and test plans, run regressions, and debug functional and performance bugs.
4. Analyze circuits for root cause analysis, investigate silicon anomalies across various conditions including PVT variations, and propose solutions.
5. Verify various IPs/Sub IPs integrated into the top-level SoC.

Requirements

1. RTL design/verification of digital circuits in Verilog.
2. Develop test benches and test cases for block-level functional verification.
3. Define verification and test plans, run regressions, and debug bugs.
4. Proficiency with EDA tools (Cadence, Mentor) and design languages including Verilog and SystemVerilog.
5. Understanding of synthesis, static timing analysis, and netlist verification.
6. UVM expertise.

Note: You must have full UK working rights to be considered for this role.

For more information, please contact Rachel Mason at IC Resources.

Additional Details

• Seniority level: Entry level
• Employment type: Full-time
• Job function: Engineering and Information Technology
• Industries: Staffing and Recruiting