Design Verification Engineer

TN United Kingdom; Bristol; Hybrid; GBP 60,000 - 85,000; Full time

Job summary

An innovative firm is seeking a Digital Verification Engineer to join their dynamic semiconductor team. In this role, you will work on the development of cutting-edge AI neuromorphic chips, focusing on the design, simulation, and verification of digital blocks implemented in RTL. Collaborating with a talented group of engineers, you will develop test benches, analyze circuit failures, and ensure the successful implementation of ASIC designs. This position offers the opportunity to contribute to groundbreaking technology that transforms trained Neural Networks into efficient silicon chips. If you have a passion for digital verification and want to be part of a forward-thinking team, this role is for you.

Qualifications

• Experience in RTL design and verification of digital circuits is essential.
• Proficiency with EDA tools and design languages is required.

Responsibilities

• Develop test benches and test cases for functional verification.
• Analyze circuits for root cause analysis and propose solutions.
• Define verification and test plans, run regressions, and debug issues.

Skills

RTL design/verification of digital circuits

Test benches and test cases development

Debugging functional and performance bugs

Root cause analysis

UVM expertise

Tools

Cadence

Mentor

Verilog

SystemVerilog

Job description

Verification Engineer

Bristol and/or fully remote within the United Kingdom.

£60,000 - £85,000 DOE

AI Neuromorphic Silicon chips

I am seeking a Digital Verification Engineer to join a dynamic fabless semiconductor team. You will be part of a wider group that will include Digital, Analog and BE Engineers and work on the development of AI neuromorphic chips. You will be responsible for the design, simulation and verification of digital block implemented in RTL for various functions including control state machine DSP, and multiple clock domain interface management.

Their technology provides fast and easy conversion of trained Neural Networks into minuscule AI silicon chips with ultra-low power consumption, low latency and small size.

Key Responsibilities

• Develop test benches and test cases for block-level functional verification.
• Work with backend/implementation teams to address synthesis, timing, DFT issues for ASIC implementation.
• Define verification and test plan, run regressions, reproduce, and debug functional and performance bugs.
• Analyse circuit for failure root cause analysis, investigate anomalous observations in silicon across various conditions, including PVT variations, and propose solutions.
• Verification of various IPs/Sub IPs integrated to top level SoC.

Requirements

• RTL design/verification of digital circuits in Verilog.
• Develop test benches and test cases for block-level functional verification.
• Define verification and test plan, run regressions, reproduce, and debug functional and performance bugs.
• Proficiency with EDA tools (Cadence, Mentor) and design languages including Verilog and SystemVerilog.
• Understanding of synthesis, static timing analysis, and netlist verifications.
• UVM expertise.

Please note: You must have full UK working rights to be considered for this role.

For more information, please contact Rachel Mason at IC Resources.