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IonQ Oxford seeks a Staff Analog Mixed-Signal Design and Verification Engineer to design analog blocks and own the full-chip model from specification to silicon validation. You will lead mixed-signal simulations (Cadence AMS, Xcelium) and drive model accuracy across the Cryo‑CMOS development flow.
You will build Verilog-A/AMS models, define abstraction levels, and ensure the model matches schematic and measured silicon while mentoring engineers in circuit design and modelling craft.
IonQ Oxford seeks a Staff Analog Mixed-Signal Design and Verification Engineer to design analog blocks and own the full-chip model from specification to silicon validation. You will lead mixed-signal simulations (Cadence AMS, Xcelium) and drive model accuracy across the Cryo‑CMOS development flow.
You will build Verilog-A/AMS models, define abstraction levels, and ensure the model matches schematic and measured silicon while mentoring engineers in circuit design and modelling craft.