Cryogenic Mixed-Signal IC Design & Modelling Lead

Clutch Canada; Oxford; Hybrid; GBP 90,000 - 140,000; Full time

Job summary

IonQ Oxford is seeking a Staff Analog Mixed-Signal Design and Verification Engineer to join the Cryo-CMOS IC team. You will design analog and mixed-signal blocks, own top-level chip integration, and build a robust mixed‑abstraction model for verification from room temperature to cryogenic conditions.

You will drive modelling standards, sign-off criteria, and collaborates across the IC development flow to ensure silicon‑faithful models and successful tape-out readiness.

Qualifications

• 10+ years of analog and mixed-signal design and modelling experience.
• Expert Verilog-A/Verilog-AMS and SystemVerilog real-number modelling.
• Proven transistor-level design of precision analog blocks (references, DACs, regulators, switches, clock distribution).
• Experience with Cryogenic silicon and tape-out flows is a plus.

Responsibilities

• Build and maintain the full-chip model used for mixed-signal simulations.
• Define abstraction levels and ensure models match schematics and measured silicon.
• Lead model-verification against schematic data and run full-chip simulations.
• Develop real-number models to enable fast digital regression.
• Set design/sign-off standards for the programme and mentor engineers.

Skills

Analog design

Mixed-signal design

Verilog-A

Verilog-AMS

SystemVerilog

Cadence flow

Mathematical modelling

Tools

Virtuoso

Spectre

Xcelium

AMS Designer

Cadence AMS Designer

Job description

IonQ Oxford is seeking a Staff Analog Mixed-Signal Design and Verification Engineer to join the Cryo-CMOS IC team. You will design analog and mixed-signal blocks, own top-level chip integration, and build a robust mixed‑abstraction model for verification from room temperature to cryogenic conditions.

You will drive modelling standards, sign-off criteria, and collaborates across the IC development flow to ensure silicon‑faithful models and successful tape-out readiness.