CPU Hardware Architect: Shape Next-Gen Architecture

European Tech Recruit; Cambridge; On-site; GBP 90,000 - 130,000; Full time

Job summary

European Tech Recruit is seeking a CPU Hardware Architect for a contractor position to contribute to a new CPU architecture. You will help define interfaces between CPU hardware, firmware and operating systems while collaborating with other architects to translate product requirements into architectural solutions.

Responsibilities include contributing to next-gen architecture, defining hardware-software interfaces, and supporting modelling and co-design activities across distributed engineering

Qualifications

• 4+ years of CPU architecture or microarchitecture experience.
• Strong understanding of ISA and assembly language.
• Knowledge of Arm, RISC-V and/or MIPS architectures.
• Understanding of modern CPU core microarchitecture.
• Software development in C, C++, assembly and/or Python.
• Experience modelling microprocessors using C/C++.

Responsibilities

• Contribute to the definition and development of next-generation CPU architecture.
• Define interfaces between hardware, firmware and operating systems.
• Collaborate with CPU architects and engineering teams on architectural specifications.
• Translate system and user requirements into practical CPU architecture solutions.
• Support modelling and analysis of processor architectures.
• Contribute to hardware/software co-design activities.

Skills

CPU architecture

C/C++

Python

Arm/RISC-V/MIPS

Microarchitecture

Distributed teams

Education

MS or PhD in Electrical Engineering or Computer Science

Job description

European Tech Recruit is seeking a CPU Hardware Architect for a contractor position to contribute to a new CPU architecture. You will help define interfaces between CPU hardware, firmware and operating systems while collaborating with other architects to translate product requirements into architectural solutions.

Responsibilities include contributing to next-gen architecture, defining hardware-software interfaces, and supporting modelling and co-design activities across distributed engineering