Senior CPU Performance Architect - Microarchitecture

European Tech Recruit; Cambridge; On-site; GBP 110,000 - 170,000; Full time

Job summary

European Tech Recruit seeks a Senior CPU Hardware Performance Architect in Cambridge to drive microarchitectural exploration and quantitative performance modeling for future high-performance processors.

You will build cycle-accurate simulators in C++/Python, profile complex workloads, and collaborate across compiler, OS, and hardware teams to shape silicon decisions and optimize throughput, power, and die area.

Qualifications

• Strong background in CPU microarchitecture and core execution structures.
• Proficient in C++ and Python for simulation and modeling tools.
• Experience in performance profiling and workload characterization.
• Understanding of PPA trade-offs in high-performance CPU design.
• Preferrred: pre-silicon performance analysis or microarchitectural pathfinding.

Responsibilities

• Own CPU performance modeling and workload characterization on-site in Cambridge.
• Develop and maintain high-fidelity C++/Python simulators to evaluate ideas.
• Quantify hardware bottlenecks and analyze throughput, power, and area.
• Collaborate with hardware and software teams to define microarchitectural specs.
• Translate workload insights into actionable hardware requirements.
• Conduct pre-silicon validation and trade-off studies.

Skills

CPU microarchitecture

C++

Python

Performance profiling

Workload characterization

Education

Master's or Bachelor’s degree in Computer Engineering, Computer Science, Electrical Engineering, or related field (or PhD)

Tools

Cycle-accurate simulators

Job description

European Tech Recruit seeks a Senior CPU Hardware Performance Architect in Cambridge to drive microarchitectural exploration and quantitative performance modeling for future high-performance processors.

You will build cycle-accurate simulators in C++/Python, profile complex workloads, and collaborate across compiler, OS, and hardware teams to shape silicon decisions and optimize throughput, power, and die area.