CPU Design Verification Engineer - (Cambridge, UK)

European Tech Recruit; Cambridge; On-site; GBP 70,000 - 110,000; Full time

Job summary

European Tech Recruit is sourcing an experienced Design Verification Engineer for a global leader in semiconductors, based in Cambridge, UK. You will work with the CPU Team to validate CPU and SOC micro-architectures, ensuring launch readiness for end products.

As a Senior CPU Verification Engineer you will develop verification plans, testbenches, and environments, lead a small team, and apply advanced techniques such as Formal, Assertions, and silicon bring-up to prove correctness across

Qualifications

• Deep knowledge of micro-processor verification functions and architectures.
• Experience leading a small verification team.
• Knowledge of Formal methods and silicon bring-up.
• Ability to develop test plans and portable testbenches.

Responsibilities

• Working with CPU and SOC Architects to understand concepts and high-level system requirements.
• Developing detailed Test and Coverage plans based on Architecture and Micro-architecture.
• Developing Verification Methodology, ensuring scalability and portability across environments.
• Developing Verification environment, including Stimulus, Checkers, Assertions, Trackers, and Coverage.
• Developing Verification Plans and Testbenches for your functional domain.
• Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions enabling all features under your care, and Debug of test failures.
• Tracking and report DV progress using metrics like Bugs and Coverage.

Skills

Microprocessor verification

RIS testing

Team leadership

Formal verification

Testbenches and transactors

Tools

Simulators

Coverage tools

Gate-level simulation

Waveform viewers

Formal proof tools

Job description

A fantastic opportunity for an experienced Design Verification Engineer to join a global leader in semiconductors, working alongside their CPU Team in Cambridge (UK).

About the Role

As a CPU Verification Engineer, Senior you will work with Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it functions to the standards of being launch ready for the end product.

Responsibilities

• Working with CPU and SOC Architects to understand the concepts and high-level system requirements.
• Developing detailed Test and Coverage plans based on the Architecture and Micro-architecture.
• Developing Verification Methodology, ensuring scalability and portability across environments.
• Developing Verification environment, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage.
• Developing Verification Plans and Testbenches for your functional domain.
• Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions enabling all features under your care, and Debug of the test failures.
• Tracking and report DV progress using a variety of metrics, including Bugs and Coverage.

What are we looking for?

• Deep knowledge of Micro-Processor Verification functions and Architectures, in domains such as: Cache Coherence, Memory ordering and Consistency, Prefetching, Branch Prediction, Renaming, Speculative execution, and Address Translation/Memory Management.
• Knowledge of Random Instruction Sequencing (RIS) and testing a given design, at the Block/Unit-level and Subsystem/Chip-level for proving correctness.
• Experience in leading a small team of Verification engineers performing CPU Verification.
• Advance techniques such as: Formal, Assertions, and Silicon bring up, is helpful.
• In-depth knowledge of Micro-processor functions, Architectures, and Micro-architectures.
• Experience in writing Test plans, portable Testbenches, Transactors, and Assembly code.
• Experience with different Verification Methodologies and Tools such as Simulators, Coverage collection, Gate-level Simulation, Waveform viewers, and Formal Proof Tools.
• Ability to develop and work independently on a Block/Unit of the design.

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