Chief Silicon Architect for AI Inference

Gradiant; United Kingdom; Remote; GBP 120,000 - 190,000; Full time

Job summary

Gradiant is seeking a leader to define our silicon direction and to build a team for model-specific inference hardware. You will collaborate with the inference research team to map models to bottlenecks and translate findings into a silicon roadmap, then lead the team through implementation, tape-out and bring-up.

You will hire and lead the initial silicon engineering team, select IP and partners, and drive performance, power, area targets across memory hierarchies and interconnects.

Qualifications

• Led architecture for a complex digital chip and delivered tape-out.
• Strong understanding of computer architecture and memory systems.
• Ability to map workload measurements to architecture decisions.
• Experience across RTL, verification, physical design and software interfaces.
• Proven ability to hire and manage a silicon engineering team.

Responsibilities

• Understand models and hardware bottlenecks with the inference research team.
• Build analytical and simulation models of microarchitectures, memory systems, dataflows, and interconnects.
• Set targets for performance, power, area, cost and reliability.
• Decide which capabilities belong in silicon, software, external IP, or partner designs.
• Develop roadmap through RTL, verification, physical design, tape-out and bring-up.
• Select IP, EDA, foundry, packaging, manufacturing and design partners.
• Hire and lead the initial silicon engineering team.
• Review microarchitecture, RTL, verification, PPA, and bring-up results.
• Define the hardware-software interface with the inference research team.

Skills

Chip architecture leadership

Tape-out experience

RTL & verification

Power & performance trade-offs

Interconnects

Team leadership

Model-driven hardware design

Job description

Gradiant is seeking a leader to define our silicon direction and to build a team for model-specific inference hardware. You will collaborate with the inference research team to map models to bottlenecks and translate findings into a silicon roadmap, then lead the team through implementation, tape-out and bring-up.

You will hire and lead the initial silicon engineering team, select IP and partners, and drive performance, power, area targets across memory hierarchies and interconnects.