Founding Silicon Engineer

Gradiant; United Kingdom; Remote; GBP 70.000 - 110.000; Vollzeit

Zusammenfassung

Gradiant is seeking a design engineer to shape model-specific inference hardware from performance modeling through RTL and verification.

You will join the initial silicon team, exploring architectures for inference workloads and turning selected designs into working silicon. You will own substantial parts of the design and wire through performance modeling, microarchitecture and verification as needed.

Qualifikationen

• Experience in at least one core area: microarchitecture, performance modeling, RTL design or verification.
• Ability to write SystemVerilog and use Python or C++ for modeling, automation and verification.
• Understanding of pipelines, memory systems, interconnects, and ASIC design flows.
• Ability to translate incomplete workload evidence into testable design questions and explain trade-offs using measurements.

Aufgaben

• Turn workload measurements into design requirements.
• Build cycle-accurate models to compare compute units, numerical formats, memory systems, dataflows, and interconnects.
• Own one or more design areas from microarchitecture through RTL implementation.
• Write test plans, build verification environments, and close functional and performance coverage.
• Use power, performance, area, and verification results to revise the design.
• Define hardware-software interfaces and the low-level execution model with the inference research team.
• Automate architecture exploration, simulation, regression testing, and analysis.
• Support emulation, tape-out, and silicon bring-up as the program advances.

Kenntnisse

Microarchitecture

Performance modeling

RTL design

Design verification

SystemVerilog

Python

C++

Jobbeschreibung

Design model-specific inference hardware from performance modeling through RTL and verification.

Why this role exists

This role will be part of our initial silicon team. The team will explore architectures for our inference workloads and turn the selected designs into working silicon.

You will own a substantial part of the design and follow it through performance modeling, microarchitecture, RTL, and verification. You do not need to be an expert in every area, but you must work across the interfaces around your design.

What you will do

• Work with the inference research team to turn workload measurements into design requirements.
• Build analytical and cycle-accurate models to compare compute units, numerical formats, memory systems, dataflows, and interconnects.
• Own one or more design areas from microarchitecture through RTL implementation.
• Write test plans, build verification environments, and close functional and performance coverage.
• Use power, performance, area, and verification results to revise the design.
• Define hardware-software interfaces and the low-level execution model with the inference research team.
• Automate architecture exploration, simulation, regression testing, and analysis.
• Support emulation, tape-out, and silicon bring-up as the program advances.

Problems you may work on

• Compute units and numerical formats for target model operations.
• Memory hierarchies for weights, activations, and KV-cache state.
• Sparse access, expert routing, and data movement.
• On-chip and chip-to-chip communication for model parallelism.
• Performance models that stay useful as the design changes.
• Verification strategies for long-running and highly parallel model workloads.

What we are looking for

• You have deep experience in at least one area: microarchitecture, performance modeling, RTL design, or design verification.
• You can work across the adjacent parts of architecture, RTL, verification, and software.
• You can write SystemVerilog and use Python or C++ for modeling, automation, and verification.
• You understand pipelines, memory systems, interconnects, and ASIC design flows.
• You can turn incomplete workload evidence into a testable design question.
• You use measured results to explain technical trade-offs.
• Tape-out or silicon bring-up experience is useful, but it is not required for every candidate.

This role is not for you if

• You want a narrowly specified block with fixed interfaces.
• You only want to focus on hardware, and are not interested in understanding models.
• You want to hand issues to another team when they cross a design boundary.
• You need a clear specification before you can start.