ASIC Verification Engineer

TN United Kingdom; Cambridge; On-site; GBP 60,000 - 100,000; Full time

Job summary

An established industry player is seeking a Senior Verification Engineer to join their rapidly growing hardware team in Cambridge. This role offers the chance to work on cutting-edge technology in quantum computing, where you'll collaborate with talented engineers to define and implement robust verification strategies. With a focus on functional verification, you'll take ownership of verification plans and develop scalable testbenches in SystemVerilog. If you're passionate about quality and performance in hardware design, this is an exciting opportunity to enhance your skills in a dynamic and supportive environment.

Qualifications

• Strong commercial experience in functional verification with ownership of verification strategy.
• Expertise in testbench design using UVM or OVM frameworks.

Responsibilities

• Define and own verification plans based on design specifications.
• Develop scalable SystemVerilog testbenches including checkers and coverage groups.
• Maintain the verification environment, tracking regressions and coverage metrics.

Skills

Functional Verification

Testbench Design

SystemVerilog Assertions (SVA)

C

C++

Python

Job description

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Senior Verification Engineer Cambridge

I am seeking a Senior Verification Engineer to join a rapidly growing HW Team in Cambridge. You will get the opportunity to work on cutting edge technology and in the area ofquantum computing. No prior experience in quantum computing? No problem. You'll learn as you go while working alongside world-class engineers in a truly cross-disciplinary environment.

About the Role As a Senior Verification Engineer, you’ll take full ownership of functional verification across their hardware systems. You’ll collaborate with a talented team of hardware designers and embedded software engineers to deliver trusted, high-performance solutions—verified from the ground up. With full visibility of the stack, you’ll define verification strategies, implement robust test environments, and ensure confidence in every design you deliver.

What You’ll Do

• Work closely with hardware designers and system architects to define and own verification plans based on design specifications
• Develop scalable SystemVerilog testbenches, including checkers, coverage groups, and reference models
• Design and run self-checking, directed, and randomized tests
• Maintain the verification environment, including tracking regressions, bugs, and coverage metrics
• Drive quality and performance across block-level and system-level designs

Core skills

• Strong commercial experience in functional verification, with ownership of verification strategy and planning
• Expertise in testbench design using frameworks like UVM or OVM
• Proficiency with SystemVerilog assertions (SVA)
• Familiarity with multiple programming languages (e.g., C, C++, Python)

Visa sponsorship will be provided for candidates who require. Please note, you must already be living and working in the United Kingdom. You must also be prepared to work onsite 3 days per week in Cambridge.

For more information, please contact Rachel Mason at IC Resources