ASIC PMU Verification Intern

Apple, Inc.; Swindon; On-site; GBP 13,000 - 20,000; Full time

Job summary

Apple, Inc. in Swindon invites students to join its PMU Hardware Tech internship, contributing to power management verification for next‑gen Apple SoCs.

You will learn from experienced Design Verification Engineers while collaborating with Design, SoC Platform Architecture, and Physical Design teams to deliver high‑quality silicon. The role emphasizes creating verification plans, developing stimulus, debugging test benches, and running simulations with RTL designs using SystemVerilog and UVM,

Qualifications

• Currently pursuing a BS, MS, or PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related field.
• End of internship you must return to school to continue education or internship must be last requirement to graduate.
• Strong familiarity with RTL design in Verilog/VHDL and logic structures; good understanding of OOP basics; experience with SystemVerilog/UVM.

Responsibilities

• Develop verification plans and stimulus for ASIC verification.
• Implement components of verification environment and debug test-bench code.
• Run simulations with synthesized netlist and analyze/debug issues.
• Collaborate with architecture and design teams to address potential issues early in the design cycle.

Skills

RTL understanding

OOP basics

SystemVerilog

UVM

analytical/problem solving

team collaboration

Education

Electrical Engineering

Computer Engineering

ECE

Tools

SystemVerilog

UVM

HDLs/HVLs

Job description

Apple, Inc. in Swindon invites students to join its PMU Hardware Tech internship, contributing to power management verification for next‑gen Apple SoCs.

You will learn from experienced Design Verification Engineers while collaborating with Design, SoC Platform Architecture, and Physical Design teams to deliver high‑quality silicon. The role emphasizes creating verification plans, developing stimulus, debugging test benches, and running simulations with RTL designs using SystemVerilog and UVM,