PMU Verification Engineer Intern - Powering Next-Gen SoCs

Apple Inc.

Swindon

On-site

GBP 12,000 - 18,000

Full time

13 days ago
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Job summary

Apple Inc. invites driven students to join the PMU Hardware Tech team for an ASIC verification internship.

You will contribute to delivering high-quality PMU silicon, work with a best-in-class verification team, and collaborate across Design, SoC Platform Architecture, and Physical Design groups. Your role includes developing verification plans, implementing test-bench components, and running simulations to ensure performance and power targets are met.

Qualifications

  • Currently pursuing BS, MS, or PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related field.
  • At the end of the internship, you must return to school to continue your education or the internship must be the last requirement for you to graduate.
  • Strong familiarity with RTL design in Verilog/VHDL and logic structures inferred; good understanding of SystemVerilog/UVM.

Responsibilities

  • Develop verification plans and stimulus; define verification strategy and completeness metrics.
  • Implement components of verification environment and debug test-bench code; assist deep design debugging.
  • Run simulations with synthesized netlists and analyze issues encountered.
  • Collaborate with architecture and design teams to address issues early in the design cycle.

Skills

RTL design (Verilog/VHDL)
SystemVerilog/UVM
OOP fundamentals
Debugging/analytical skills

Education

Bachelor's, Master's or PhD in Electrical/Computer Engineering

Job description

Apple Inc. invites driven students to join the PMU Hardware Tech team for an ASIC verification internship.

You will contribute to delivering high-quality PMU silicon, work with a best-in-class verification team, and collaborate across Design, SoC Platform Architecture, and Physical Design groups. Your role includes developing verification plans, implementing test-bench components, and running simulations to ensure performance and power targets are met.

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