Senior UVM Verification Engineer

TN France; Grenoble; Sur place; EUR 45 000 - 75 000; Plein temps

Résumé du poste

An established industry player in the Grenoble area is seeking a Senior UVM Verification Engineer to join their dynamic team. This role offers the opportunity to work on exciting R&D projects, focusing on developing verification environments using SystemVerilog and UVM methodology. You will also play a crucial role in training fellow engineers, fostering a collaborative and innovative environment. If you have a strong background in IP or SoC verification and are looking to advance your career in a friendly setting, this is the perfect opportunity for you. Join a team that values expertise and growth!

Qualifications

• 3-5+ years of experience in IP or SoC verification.
• Confident knowledge of SystemVerilog and UVM methodology.

Responsabilités

• Responsible for R&D projects and developing verification environments.
• Providing training to other engineers.

Connaissances

IP or SoC verification experience

SystemVerilog

UVM methodology

SoC architecture

bus communication protocols (AMBA / AXI)

OOP skills

scripting skills (Perl / Shell / Python / C)

Fluent English

Fluent French

Formation

Master's Degree

Description du poste

Senior UVM Verification Engineer, Grenoble

Are you looking for the next step in your career in UVM Verification? Would you like to learn from skilled experts in a friendly and growing environment with exciting projects? If the answer is yes, then this may be the perfect opportunity for you!

I have a key requirement for an experienced/senior Verification Engineer to work for an established company based in the Grenoble area, focusing on design and verification services for major clients.

As a senior verification engineer, you will be responsible for R&D projects, developing verification environments (SystemVerilog / UVM), VIP components, and providing training to other engineers.

Technical Skills

• 3-5+ years' IP or SoC verification experience
• Confident knowledge of SystemVerilog and UVM methodology
• SoC architecture
• Knowledge of bus communication protocols - AMBA / AXI, etc.
• OOP (Object-Oriented Programming) and scripting skills / hardware & software - Perl / Shell / Python / C
• Fluent English - and preferably French
• Master's Degree - a bonus

If you would like to know more, please contact Rob Hudson at IC Resources for a discussion.