Senior NoC Power & Interconnect Solutions Engineer

Qualcomm; Guyancourt; Sur place; EUR 80 000 - 110 000; Plein temps

Résumé du poste

Qualcomm France S.A.R.L. is seeking an experienced engineer to join the Solutions Deployment Team within the Engineering Group ASICS to deploy and support QITC NoC technology across Qualcomm SoCs.

This role offers exposure to mobile, automotive, servers and IoT platforms. You will work with architecture, hardware, software, verification and post-silicon teams to define interconnect requirements, resolve power issues, and validate new NoC power architectures while contributing technical training

Qualifications

• Master’s degree in Microelectronics, Computer Science, or related field with 3–5 years in SoC/ASIC development.
• Bachelor’s or Master’s degree with 4+ years in ASIC design, verification, validation, integration.
• PhD with 2+ years in ASIC-related roles.

Responsabilités

• Collaborate with Architecture, Hardware, software, verification, emulation; ensure NoC tech is used efficiently across Qualcomm SoCs.
• Define interconnect requirements and configuration for various SoCs.
• Provide support on power issues and NoC power unit integration.
• Resolve NoC power micro-architecture and validate new power architectures.
• Develop technical materials and training for global teams.

Connaissances

SoC development flow

SoC architecture

RTL design

verification

Power optimization

NoC concepts

interconnect protocols

strong communication

Formation

Master’s degree in Microelectronics, Computer Science, or related field

Bachelor’s degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Description du poste

Qualcomm France S.A.R.L. is seeking an experienced engineer to join the Solutions Deployment Team within the Engineering Group ASICS to deploy and support QITC NoC technology across Qualcomm SoCs.

This role offers exposure to mobile, automotive, servers and IoT platforms. You will work with architecture, hardware, software, verification and post-silicon teams to define interconnect requirements, resolve power issues, and validate new NoC power architectures while contributing technical training