Senior RTL Design Engineer

European Tech Recruit; Paris; Hybride; EUR 70 000 - 90 000; Plein temps

Résumé du poste

A tech recruitment firm is seeking a Senior RTL Design Engineer based in Paris or Zurich. In this role, you will design and implement crucial digital blocks, working collaboratively across software, architecture, and verification teams to develop cutting-edge chipsets. The ideal candidate has over 5 years of ASIC/FPGA experience and proficiency in SystemVerilog or VHDL among other skills.

Qualifications

• 5+ years in ASIC / FPGA development.
• Proficient in SystemVerilog, Verilog, or VHDL.
• Solid grasp of clock domains, low-power design, and design optimization.

Responsabilités

• Design and implement RTL for key digital components.
• Define micro-architectures and optimize for power, performance, and area.
• Integrate, test, and debug top-level designs.
• Support verification, documentation, and planning.
• Evaluate and integrate third-party IP.

Connaissances

ASIC / FPGA development

SystemVerilog

Verilog

VHDL

Low-power design

Design optimization

Scripting in Python

Unix / Linux environments

Git

SVN

Outils

Lint

CDC

RDC

Description du poste

Senior RTL Design Engineer

Paris, France or Zurich, Switzerland

Join a company that blends two decades of experience with the energy of a start-up. We’re building the next generation of chipsets - and you’ll be at the heart of it.

As a Senior RTL Design Engineer , you’ll drive the design and implementation of critical digital blocks. You'll collaborate across software, architecture, and verification teams to bring advanced silicon solutions to life.

What You’ll Do

• Design and implement RTL for key digital components
• Define micro-architectures and optimize for power, performance, and area
• Integrate, test, and debug top-level designs
• Support verification, documentation, and planning
• Evaluate and integrate third-party IP

What You Bring

5+ years in ASIC / FPGA development.

Proficient in SystemVerilog, Verilog, or VHDL

Solid grasp of clock domains, low-power design, and design optimization

Experience with front-end tools (Lint, CDC, RDC)

Comfortable in Unix / Linux environments; scripting in Python, Tcl, or Shell

Familiar with Git or SVN

Interested to know more?

Apply here with your CV .

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