Senior RTL Design Engineer

Sequans Communications; Paris; Hybride; EUR 60 000 - 90 000; Plein temps

Résumé du poste

A leading company in the IoT and 5G industry is seeking a skilled digital design engineer. You will work within a vibrant, multicultural team, responsible for the design and verification of digital blocks for chipsets. Candidates should have significant experience in ASIC/FPGA development and strong skills in hardware description languages. The position includes opportunities for remote work and an engaging work environment with various team tasks.

Prestations

Remote work options

On-site gym

Company restaurant

Qualifications

• 5+ years experience in ASIC and/or FPGA development.
• Strong command of SystemVerilog / Verilog / VHDL.
• Fast learning, autonomous, excellent communication skills.

Responsabilités

• Design (RTL coding) of key digital building blocks.
• Planning, Tracking and reporting of activities.
• Contribute to integration, testing and debugging.

Connaissances

Hardware description languages

Optimization techniques

Unix environment

Version control systems

Formation

Degree (BSc / MSc / PhD) in computer science, electrical engineering or equivalent

Outils

Git

SVN

Description du poste

Looking to join a company that combines 20 years of experience with a startup mindset? Work with teams across the globe, enjoy one remote day per week, access our on-site gym and company restaurant — all in a vibrant, multicultural environment that's always on the move.

Within the VLSI team , your responsibilities will be to specify, design, implement and verify various digital blocks linked to Sequans’ next chipsets generation. You will work closely with our software, signal processing algorithms, architecture, integration and verification teams and you will be responsible for planning, tracking and reporting activities related to the implementation of your digital blocks.

More specifically your responsibilities will be as follows :

• Design (RTL coding) of key digital building blocks.
• Requirements analysis and micro architecture (uarch) definition.
• Design optimization in the context of timing, power and area.
• Contribute to top-level integration, testing and debugging.
• Planning, Tracking and reporting of key activities.
• Preparing documentation and technical reports.
• Supporting verification and debugging.
• Third party IPs evaluation.

We are looking for candidates with the following experience and skills :

• Degree (BSc / MSc / PhD) in computer science, electrical engineering or equivalent studies.
• At least 5 years of working experience in ASIC and / or FPGA development.
• Strong command of hardware description languages (SystemVerilog / Verilog / VHDL).
• Background in optimization techniques for high throughput, low area, low power designs.
• Experience in multiple clock domains architectures.
• Experience in Front End activities (e.g Lint, CDC, RDC tools).
• Familiarity with Unix environment and shell programming / scripting (C-Shell, Tcl, Python).
• Experience in version control systems (Git, SVN).

The following skills will be considered as bonus :

• Knowledge of synthesis and static timing analysis tools.
• Knowledge of Place and Route.
• Experience in 3rd-Party IPs integration (NoC, RISC-V, memories, peripherals, etc).
• Exposure to LTE-M / NB-IoT, 4G LTE Cat 1bis, 5G NR.

The ideal candidate profile would be as follows :

• Fast learning capabilities, highly motivated, self-starter, autonomous
• Ability to work in a fast moving and multicultural environment
• Excellent written and oral communications skills, fluent English

At Sequans, we know that our success depends on our people, so we are always on the lookout for innovators, leaders, and visionaries. Our team is driven by a shared desire to lead in the IoT / 5G industry. We are looking for highly motivated team players with ideally records of achievement in wireless technologies to help us maintain and develop our leadership in the IoT / 5G industry. Throughout the year, we are regularly recruiting talented candidates with competencies in software development, software validation, software integration, digital signal processing, RF and digital chip design, hardware design and test.