Senior FPGA Architect for Space Gateware

Blackshark; Toulouse; Sur place; EUR 90 000 - 120 000; Plein temps

Résumé du poste

Aerospacelab in Toulouse is seeking a Senior FPGA Engineer to take technical ownership of gateware and architect FPGA designs across units. You will mentor engineers, drive trade-offs, and ensure robust verification for on-board computers, software defined radios, and sensors.

You will collaborate with EE, embedded software, RF and network teams, translating system intent into reliable FPGA solutions and shaping state-of-the-art gateware for orbit-ready systems.

Qualifications

• 5 to 10 years of professional FPGA/RTL design experience.
• Master or PhD in Computer, Electronics or Mechatronics Engineering or equivalent.
• Strong command of RTL programming (in order of preference: VHDL, Verilog, SystemC, SystemVerilog).
• Experience with C and Python.
• Strong understanding of the full FPGA design flow (synthesis, place & route, timing closure).
• Strong understanding of software and hardware interactions.
• Excellent verbal and written skills to interact across teams and up to system level.

Responsabilités

• Define and own the FPGA design architecture from system requirements, including major design trade-offs.
• Design, simulate, integrate and test RTL code while reviewing the RTL of others.
• Drive the verification strategy (testbenches, on-target test procedures, CI).
• Write and test software driver code.
• Write and review technical documentation.
• Mentor junior and mid-level engineers, and lead small FPGA teams.
• Interface with other engineering teams (EE, RF, Operations, Embedded Software, System).

Connaissances

RTL design

VHDL/Verilog

SystemC/SystemVerilog

Python

C

FPGA design flow

English (good)

Mentor engineers

Formation

Master's or PhD in Computer/Electronics/Mechatronics

Outils

QuestaSim

Makefile

Python

TCL

GitLab

Docker

Embedded-C

Embedded-Linux

Description du poste

Aerospacelab in Toulouse is seeking a Senior FPGA Engineer to take technical ownership of gateware and architect FPGA designs across units. You will mentor engineers, drive trade-offs, and ensure robust verification for on-board computers, software defined radios, and sensors.

You will collaborate with EE, embedded software, RF and network teams, translating system intent into reliable FPGA solutions and shaping state-of-the-art gateware for orbit-ready systems.